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Contributor
Contributor
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Registered: ‎01-27-2016

Polyphase filter delays- behavioral versus place and routed design

I am implementing a polyphase filter bank with the fir compiler core. I use 512 sets of coefficients and cycle through them under control of an NCO to implement an interpolation continuously variable rate change. I posted earlier to the forum about using the fir compiler to implement this filter.

https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/Implementation-of-polyphase-filter-bank/m-p/1116882#M11634

I have the design working in a behavioral simulation, however now that I have implemented the design on our board with an Artix7 200t device the behavior has changed. I suspect the pipeline delay of the filter bank has changed relative to what I was seeing in behavioral simulation.

For my continuously variable rate design the delay through the FIR filter must be known as I have to align a valid sample enable generated by the NCO with the proper output interpolant as the NCO creates an punctured enable that must be aligned to the samples that are to be retained and used downstream.

Is there a way to find out the delay through the filter, both delays based on the input enable and delays just based on the clock?

I know I can apply an impulse to the filter input and provide a set of filter coefficients with a single non-zero value and determine it, but I was hoping this information was available somewhere. Thanks.

 

Bill

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Explorer
Explorer
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Registered: ‎01-27-2008

@centercitybill 

Perhaps add the TUSER and place a marker in the data once in a while or a counting pattern, then determine latency by clocks it takes for TUSER input to output.

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