03-25-2020 05:32 PM
I am chasing a weird bug. I have a design with 4 identical banks of 4 cascaded low-pass decimation filters, using the Xilinx FIR generator. Each filter in the chain can be individually bypassed.
In simulation all of the filters behave as expected.
In hardware I inject a synthetic signal into each filter, one at a time. I am putting the same signal into each bank. At the output of the system, I can see that the first two filters in the chain do not have the expected filter response:
My first thought was that there was a synthesis optimization problem. However, I spent considerable time setting up a post-route simulation, and the results look great even in the post-route sim.
I have tested on different boards, and both have the same issue with the first two filters. Therefore I am ruling out hardware/chip problems.
My questions are:
And most importantly:
Any ideas about what might be going on? What can I look at to try to debug this?
04-17-2020 08:43 AM
The filters are connected:
D3 -> D10 -> D2 -> D4
Each filter has a bypass mux and some saturation logic. This chain is replicated 4 times.
After considerable time I was able to narrow down the cause of the problem, although I am still baffled about the mechanics. It seems the problem was introduced by switching from "Area" optimization to "Speed" optimization. There were several other changes made at the same time, but reverting that change seemed to fix it. Only D3 and D10 were effected. They are also the only filters that are configured to take a sample each cycle.
My hypothesis is that one of the speed optimizations (I didn't take the time to figure out which one) is wiring up the DSP48s in an unsupported configuration that is not represented by the simulation model. Maybe some sort of reset condition? That could explain why the behavior was different in each chain for each power cycle.