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Visitor
Visitor
10,682 Views
Registered: ‎05-05-2008

Problem with Blackbox and clock signal in System Generator

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Hello:

 

I want to introduce VHDL code at Simulink using the Black Box of System Generator but when I import the VHDL code into the black box I dont know how to put the FPGA clock (which i set at System Generator block) at the clock input of mi black box. 

 

Could somebody help me please?

 

Thank you very much, and good bye.

 

luis ( ) 

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Explorer
Explorer
13,126 Views
Registered: ‎09-28-2007
When you import your VHDL module through a Black Box, the module should have appropriate clock and clock enable pairs. System Generator automatically wires the clock and clock enable pairs to the system clock pin (as specified in the System Generator compilation dialog) and appropriate clock enable generator during netlisting.
 
The requirements on clock and clock enable pairs is documented in the System Generator User Guide under section "Black Box HDL Requirements and Restrictions":
 
An HDL component associated with a black box must adhere to the following System Generator requirements and restrictions:
  •  
    • Any port that is a clock or clock enable must be of type std_logic. (For Verilog black boxes, ports must be of non-vector inputs, e.g., input clk.)
    • Clock and clock enable ports in black box HDL should be expressed as follows: Clock and clock enables must appear as pairs (i.e., for every clock, there is a corresponding clock enable, and vice-versa). Although a black box may have more than one clock port, a single clock source is used to drive each clock port. Only the clock enable rates differ.
    • Each clock name (respectively, clock enable name) must contain the substring clk, for example my_clk_1 and my_ce_1.
    • The name of a clock enable must be the same as that for the corresponding clock, but with ce substituted for clk. For example, if the clock is named src_clk_1, then the clock enable must be named src_ce_1.
 

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Explorer
Explorer
10,677 Views
Registered: ‎07-27-2009

Luis_ml,

 

Do you want to import VHDL into simulink or do you want to use some simulink generated VHDL in your FPGA?

 

Guessing you want to import VHDL in the FPGA, what you need to do is write a toplevel module around the generated VHDL and use components, port maps etc (consult a VHDL book - section structural VHDL) to connect pins and clocks of the FPGA to the generated VHDL module. Read in the generated VHDL together with the toplevel (or use the generated VHDL as toplevel entity) and run synthesis etc. You can first simulate your design to check for functional correctness.

 

Does this help?

 

Cheers!

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Explorer
Explorer
13,127 Views
Registered: ‎09-28-2007
When you import your VHDL module through a Black Box, the module should have appropriate clock and clock enable pairs. System Generator automatically wires the clock and clock enable pairs to the system clock pin (as specified in the System Generator compilation dialog) and appropriate clock enable generator during netlisting.
 
The requirements on clock and clock enable pairs is documented in the System Generator User Guide under section "Black Box HDL Requirements and Restrictions":
 
An HDL component associated with a black box must adhere to the following System Generator requirements and restrictions:
  •  
    • Any port that is a clock or clock enable must be of type std_logic. (For Verilog black boxes, ports must be of non-vector inputs, e.g., input clk.)
    • Clock and clock enable ports in black box HDL should be expressed as follows: Clock and clock enables must appear as pairs (i.e., for every clock, there is a corresponding clock enable, and vice-versa). Although a black box may have more than one clock port, a single clock source is used to drive each clock port. Only the clock enable rates differ.
    • Each clock name (respectively, clock enable name) must contain the substring clk, for example my_clk_1 and my_ce_1.
    • The name of a clock enable must be the same as that for the corresponding clock, but with ce substituted for clk. For example, if the clock is named src_clk_1, then the clock enable must be named src_ce_1.
 

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Observer
Observer
8,110 Views
Registered: ‎04-25-2013

HI

Thanks and Regards
Teja
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Visitor
Visitor
6,885 Views
Registered: ‎09-29-2014

hello, i couldn't find where my mistake is. in verilog code, simulink detects fpga clock and clock enable and automatically wires "clk" and "ce". but in the VHDL code, it does not recognize my "clk" and "ce" pins. 

 

can u help me?

 

---

module test(clk,ce,y,c,m );
input clk;
input ce;
input [7:0] m,c;

output reg [31:0] y;

 

integer x;

initial
begin
x=0;
end

always @(posedge clk)
begin
x = x+1;
y = m*x+c;
end
endmodule

---

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

 

entity testVhd is

Port ( clk,ce : in STD_LOGIC;
m,c : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (31 downto 0));
end testVhd;

 

architecture Behavioral of testVhd is

subtype slv is std_logic_vector;
subtype unsgn is unsigned;

signal x : integer := 0;

begin

process(clk)
begin
if (clk'event and clk='1') then
x <= x+1;
y <= slv(unsgn(m)*to_unsigned(x,24) + unsgn(c));
end if;

end process;

end Behavioral;

 

VerilogvsVHDL.PNG
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Visitor
Visitor
6,786 Views
Registered: ‎09-29-2014

@akgulb wrote:

hello, i couldn't find where my mistake is. in verilog code, simulink detects fpga clock and clock enable and automatically wires "clk" and "ce". but in the VHDL code, it does not recognize my "clk" and "ce" pins. 

 

can u help me?

 

---

module test(clk,ce,y,c,m );
input clk;
input ce;
input [7:0] m,c;

output reg [31:0] y;

 

integer x;

initial
begin
x=0;
end

@always @(posedge clk)
begin
x = x+1;
y = m*x+c;
end
endmodule

---

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

 

entity testVhd is

Port ( clk,ce : in STD_LOGIC;
m,c : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (31 downto 0));
end testVhd;

 

architecture Behavioral of testVhd is

subtype slv is std_logic_vector;
subtype unsgn is unsigned;

signal x : integer := 0;

begin

process(clk)
begin
if (clk'event and clk='1') then
x <= x+1;
y <= slv(unsgn(m)*to_unsigned(x,24) + unsgn(c));
end if;

end process;

end Behavioral;

 


 

anybody has an idea?? 

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Visitor
Visitor
6,665 Views
Registered: ‎10-21-2014

I have exaclty the same problem, I am not able to get the new clk name recognized... Help please

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Observer
Observer
3,873 Views
Registered: ‎03-23-2016

The CLK and CE are connected, but the connection is abstracted so you can't see them.  The CLK is connected to your system clock as you have defined in your system generator token.  I don't know what the CE is connected to, perhaps tied to '1'?  I'm trying to figure out how to edit the .m file to show the CE pin so I can make a connection to that.

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


.

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Newbie
Newbie
261 Views
Registered: ‎09-24-2020

Hi,

Please mention clock and clock enable as below in your VHDL code. It automatically detects.

I had same issue and with help of my colleague I solved it.

port (
clk : in std_logic;
ce : in std_logic;

Thanks.

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