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Registered: ‎03-26-2009

Problem with simulation clock when importing netlist as blackbox in Sysgen 12.2



I have a problem with Sysgen model that contain a blackbox.


  • The blackbox uses a wrapper to instantiate a netlist. It doesn't use the clock enable (CE) port, so it is unconnected.
  • The problems happen when I include blackbox in a multirate system, but it works smothly with single rate simulation/models.

I've replicated the problem using Sysgen User Manual example.

Chapter 4 "Importing HDL Modules", example 2: "Black Box Tutorial Example 2: Importing a Core Generator Module that Needs a VHDL Wrapper to Satisfy Black Box HDL Requirements"



The code is attached. There is a version "coregen_import_example2.mdl" that works fine (following exactly the user manual instructions) and there is other with the problem I want to solve: "coregen_import_example2_blackbox_problem.mdl"

The difference is the simulation clock as shown in the figure:


Double Clock Rate Simulation


Despite the incoming signal at the filter black box is the same, the filter black box now works internally at 2x the expected frequency. I understand it is not a bug, and the problem is that the black box doesn't use the CE port. But how could I solve it? Could anyone give an example to add CE control to the _wrapper.vhd?


I can't modify the netlist that I want to include in the sysgen model, so I think there must be included a CE control logic that handles netlist clock. Any other idea is very welcome.


Thanks in advance!


Best regards,

Jose M.



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Xilinx Employee
Xilinx Employee
Registered: ‎07-11-2011

Re: Problem with simulation clock when importing netlist as blackbox in Sysgen 12.2



I think there are some limitations for Clock Enable pors usage.

Please refer "The Clock Enables Option"  section of UG640 or the Vivado User Guide of your respective tool verison for more details and usage


Please do google search before posting, you may find relavant information.
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