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Registered: ‎01-12-2014

Pulse generator with programmable duty cycle



I am new to the whole System Generator environment, but I am trying to generate a signal generator (PWM) where I can programm the duty cycle via software from SDK.


My design is quite simple, I have a counter, and two relational blocks.

I use the relational block to reset the counter when it reaches the specified 8 bit constant, while I use the second relational block to decide the duty cycle of my PWM signal.

After this I have just connected a mux where I use my PWM signal to convert the whole wave to 14 bits values (0 -1) to send to a DAC connected to the FMC pins of my VC707 eval board.


I thought it may be possible to send the two values for the relational blocks via "From register" blocks, but actually once I have generated my IP Core I saw that there are some C functions to initialize the block and make it work.


Actually there are two things that are not really clear to me at the moment:


The first is: my IP Core seems to have two inputs and one output (as expected), I would connect the 14 bits output to the DAC , but there should be my inputs be connected?

The second  question is: the IP Core drivers are showing the base address of the IP Core inside the uBlaze system but this is address in memory for a 64 KB space, how can I go from this to my two "From Register" blocks?

For instance, if I have just two "From register" blocks, and the device base address is 0x72600000, and I have two 8 bit registers, should the addresses be 0x72600000 and 0x72600040?


I would need a quick tip to test If am able to test this block then via SDK application, or if at least there is a way to keep this simple and working.




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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

You need to DDS compiler core in SDK environment.

DDS core used to generate sine/cosine output based on input values .

DDS is primarily designed for sine, cosine and phase generation, applications include phase and frequency modulation.

Variable frequency Square may be generated using level threshold approach by taking MSB of phase_out
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