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1,048 Views
Registered: ‎11-07-2018

Question about FFT 9.1 IP

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Hello,

I upgraded the FFT 7.1 Logicore IP to FFT 9.1. Some of the older ports have become obsolete or renamed and new ports have been added. My question is regarding the output pin edone. This has become obsolete in 9.1 FFT but my logic requires it to be used. 

 

What pin can I use as an edone port? 

 

Regards,

Vanshika Chawla

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Moderator
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1,015 Views
Registered: ‎08-16-2018

Re: Question about FFT 9.1 IP

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@vanshika_chawla

 

In FFT 7.1,  EDONE goes High one clock cycle immediately prior to DONE going High; and DONE goes high for one clock cycle when the transform calculation has completed.

Similarly, In FFT 9.1, "m_axis_data_tvalid" is asserted by the core when it is able to provide sample data at the output.

May be you can use this port as a replacement for EDONE/DONE. 

 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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Moderator
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1,016 Views
Registered: ‎08-16-2018

Re: Question about FFT 9.1 IP

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@vanshika_chawla

 

In FFT 7.1,  EDONE goes High one clock cycle immediately prior to DONE going High; and DONE goes high for one clock cycle when the transform calculation has completed.

Similarly, In FFT 9.1, "m_axis_data_tvalid" is asserted by the core when it is able to provide sample data at the output.

May be you can use this port as a replacement for EDONE/DONE. 

 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
984 Views
Registered: ‎11-07-2018

Re: Question about FFT 9.1 IP

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Hello,

Thanks for the reply. According to the 9.1 datasheet for FFT, DV is renamed to m_axis_data_tvalid. I require to use DV as well in my code.

Should all logic connected to edone, done and dv earlier, be connected to m_axis_data_t_valid now ? Will it work with state machines and timing ?

Won't the EDONE, DONE and DV ports have problems if merged to one single port?

Additionally, m_axis_data_tvalid should map onto EDONE in a cycle accurate fashion i.e. it should go high or low at the same edge as edone.

 

Regards,

Vanshika

 

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Moderator
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Registered: ‎08-16-2018

Re: Question about FFT 9.1 IP

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I do not think that merging ports is a good idea.

Further, you can see the topic "How to Migrate from Fast Fourier Transform 7.1 to Fast Fourier Transform 9.1" at  page 163 of below document. Figure is not clear, I will try to get the correct figure,

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug958-vivado-sysgen-ref.pdf


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
845 Views
Registered: ‎11-07-2018

Re: Question about FFT 9.1 IP

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Thanks for the pdf document. Can you attach a clearer picture?

-Vanshika

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