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chili.chips
Participant
Participant
1,614 Views
Registered: ‎09-01-2014

RFDC-Eval

We have purchased ZCU111 and have successfully brought it up with RFDC-Eval GUI, both 2018.3 and 2018.2 version.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/57606309/ZCU111+RFSoC+RF+Data+Converter+Evaluation+Tool+Getting+Started+Guide#ZCU111RFSoCRFDataConverterEvaluationToolGettingStartedGuide-UIInstallation

  Then, for in-depth evaluation, we've followed Xilinx instructions to enable external clocking, essentially bypassing on-board PLLs from TI.

 That has however rendered RFDC-Eval tool inoperable.

  On the other hand, using RF-Analyzer tool, we were able to prove that the external clock was successfully applied, as well as perform ADC acquisitions and DAC generations. Compared to RFDC-Eval, the capabilities of RF-Analyzer are limited:

1) supports only JTAG, thus slow communication with board

2) has only BRAM for data storage, thus cannot do larger sample sizes that the DDR mode of RFDC-Eval offers

3) cannot set 32mA DAC mode from within GUI

  That brings us back to RFDC-Eval tool. The problem we've seen with it post-external-clock mod is:

  •       Communication with board is broken, both Ethernet and JTAG

   That seems to have to do with 'rftool' (invoked from 'autostart.sh') not completing due to failure of TI PLL status check, which then does not start 'rftrd' service that the tool communicates with. It feels like the tool was never tested with External Clock Modification.

    Need your help to get around this roadblock. We suspect a minor SW patch would do...

JTAGJTAGEthernetEthernetrftool hangrftool hang

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fernandovives
Adventurer
Adventurer
1,576 Views
Registered: ‎12-16-2018

Hi 

The malfunction of RF Analyzer could be a symptom of another problem. The fail of both debug interfaces could be a problem in the board produced by a bad clock signal. Check the following:

I) Make sure that the external clock have an acceptable jitter.

I) The voltage level of the signal is in range.

I) The clock period is between the max and minimum clock period of the device.

A simple way to check this is generate a clock signal equal that the signal present in the board and test the RF Analyzer. 

Let me know if you can fix this issue

fernandovives
Adventurer
Adventurer
1,566 Views
Registered: ‎12-16-2018

Also check the page number 50 of the UG1271 about provide SYSREF clock with the onboard optional SMA. Xilinx recommend modify the circuit of the board to place capacitors for the SMA clock connector.

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chili.chips
Participant
Participant
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Registered: ‎09-01-2014

thanks, while checking for that, is there a switch we could pass to 'rftool' command to make it ignore errors from TI clock chips, as well as clock errors in general?

  • That would be to decouple Board Communication from Data Converter clocking and so enable the use of RFDC-Eval tool for clock diagnostics

It's good that the RF-Analyzer does not have such depenedency and, while slow and with incomplete feature set, its Tile Status window and 'Clock Detected' indicator within it are very helpful.

So, the RF-Analyzer shows green 'Clock Detected' for both DAC tiles and first two ADC tiles. We have ineed not applied clock to the remaining two ADC tiles...

 

 

 

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fernandovives
Adventurer
Adventurer
1,545 Views
Registered: ‎12-16-2018

Hi

The  onboard clocking options are only available in the RF evaluation tool, in my best of knowledge there is not a command or option to ignore the clocks errors, if you can find this option let me know. At the bottom of the page  23 of UG1309 exist a brief explanation about the connection requirements of an external clock.

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chili.chips
Participant
Participant
1,527 Views
Registered: ‎09-01-2014

we need External Clocking for RFDC-Evaluation tool. From UG1301 User Guide, that is a valid clocking option, yet it's apparently causing communication errors with board.

   Q) Why would RFDC-Evaluation tool report communication error for Ethernet or JTAG with external ADC/DAC clock, but not with internal? How is ADC/DAC clock related to Ethernet or JTAG operation?

     RF-Analyzer tool for the exact same external ADC/DAC clock communicates over JTAG with no problem. Moreover, our external 3GHz clock is recognized by ADC/DAC and, within RF-Analyzer, we can produce DAC waves using our 3GHz external clock, as well as acquire ADC signals  using our 3GHz external clock.

   If it was not for its limited sample size, the RF-Analyzer would have been sufficient and we would not have been spendign any more time with RFDC-Evaluation tool

  • If you could provide RF-Analyzer Vivado source project for us to increase BRAM size to support 64K samples, then the RF-Analyzer would do. It's inability to set DAC to 32mA output its tolerable for us

 

RFDC-Eval.PNG

 

 

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fernandovives
Adventurer
Adventurer
1,512 Views
Registered: ‎12-16-2018

Hi 

Isn't possible to me right now provide to you a Vivado project because I don't have Vivado 2018.x on my personal laptop and I'M far from my research center. I will provide you a Vivado project as soon as possible to me

chili.chips
Participant
Participant
1,487 Views
Registered: ‎09-01-2014

... when you get to it, pls. also send any relevant AppNotes you may have on that topic, esp. wrt how to make RF-Analyzer S/W recognize the new, enlarged sample storage in underlining FPGA design.

  • 64K samples for DAC and 16K samples for ADC is what we are looking for

An awesome bonus would be if you could take a stab of your own at modifying design to allow that :-)

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