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Registered: ‎01-31-2019

Recommended references for writing a DSP IP core in Vivado.

Hello everyone,, So I am working with an SDR system and part of the system lives on my FPGA (zedboard). I am trying to offload the DSP (Binary Phase Shift Keying of IQ samples) to an IP core. I know some verilog, but have really just been using the IP integrator tool in Vivado to prepare my hardware so I can code in C. My questions are 1)Should I look into Vivado HLS for coding DSP cores? (does it cost extra) -My vague understanding of HLS is that it turns C code into a processing core in Vivado. 2) Or should I just be doing this in straight verilog and adding it to a custom IP core? For either method, any reference material (book recommendations) that I can use to learn how to achieve this stuff would be immensely appreciated. **I'm at the point where I wouldn't mind spending a few weeks just sitting down and teaching myself from a textbook.** I'm really looking for the method that can cut some of my development time down and would love the opinion of those who have worked with DSP cores/Vivado in general.
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Scholar dgisselq
Registered: ‎05-21-2015

Re: Recommended references for writing a DSP IP core in Vivado.


Sorry, I have no experience with HLS, so I can't say how free or expensive it is.

I can say that there are a lot of good DSP references on ZipCPU.com.

Let's walk through some of the steps necessary in demodulating a BPSK stream:

  1. You'll need to downconvert it to baseband.  Here's an article on how to build an NCO.
  2. You'll need to apply a matched filter.  Depending on the speed of your BPSK signal, you may need a high speed filter implementation or a lower speed implementationHere's an example of one that crosses between the two, and downsamples at the same time.
  3. You'll need to track baud rate and carrier frequency.  Here's an article on how to build a PLL from logic that can be used for that purpose.

Hopefully that'll get you off, started on the right foot too.


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Registered: ‎10-18-2018

Re: Recommended references for writing a DSP IP core in Vivado.


Writing custom IPs using HLS takes surplus amount of FPGA resources. Better use HDL for writing your own logic. Try using inbuilt IPs or go for "OpenCores" wherein such IPs are available for free. Better study "Digital Signal Processing with FPGA by Uwe Meyer-Baese" if you want to explore more.

And that username of yours, is really very shiney! I hope you go to Goa soon.




Best Regards,
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