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Visitor pg1003
Visitor
844 Views
Registered: ‎05-31-2018

Regarding Xilinx GATEWAY IN Block in Simulink

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Hi. I am facing a problem while using Xilinx blockset in Simulink. I am feeding an ECG input signal to the "GATEWAY IN" Block and at the output of the "GATEWAY IN" Block, my signal get distorted. I am attaching the input as well as output signal for your reference.     I want my output signal same as input signal. I feel this problem is due to sample period value selected in "GATEWAY IN" Block. This GATEWAY IN block does not take value less than 1 and due to it, the output is not the same as input. Kindly help.

Input_to_the_Gateway IN_Block.png
Output_of_Gateway IN_Block.png
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Participant caccolillo
Participant
1,041 Views
Registered: ‎09-09-2010

Re: Regarding Xilinx GATEWAY IN Block in Simulink

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Have a look at the xilinx system generator token, in the "clock" panel.

You should find the relationship among system clock and simulink period.

 

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3 Replies
Participant caccolillo
Participant
1,042 Views
Registered: ‎09-09-2010

Re: Regarding Xilinx GATEWAY IN Block in Simulink

Jump to solution

Have a look at the xilinx system generator token, in the "clock" panel.

You should find the relationship among system clock and simulink period.

 

View solution in original post

Visitor pg1003
Visitor
751 Views
Registered: ‎05-31-2018

Re: Regarding Xilinx GATEWAY IN Block in Simulink

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Thanks a lot Sir. It is working to a great extent. I am still fine tuning it.
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Visitor pg1003
Visitor
736 Views
Registered: ‎05-31-2018

Re: Regarding Xilinx GATEWAY IN Block in Simulink

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It is working. I am getting desired signal at the output of GATEWAY IN block. Thanks a lot.
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