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Visitor pg1003
Visitor
910 Views
Registered: ‎05-31-2018

Regarding xilinx blockset addsub module

Hi, I am designing a system using XILINX BLOCKSET toolbox. While doing simulation, my addsub module is shown as below in the image. I want to know why it happens and what can be done to improve it.
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3 Replies
Visitor pg1003
Visitor
904 Views
Registered: ‎05-31-2018

Re: Regarding xilinx blockset addsub module

The module contents a+b(!) become red with exclamation sign. I am unable to upload the figure.
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Visitor pg1003
Visitor
898 Views
Registered: ‎05-31-2018

Re: Regarding xilinx blockset addsub module

Also I want to know whether it has any effect on the result.
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Teacher eilert
Teacher
849 Views
Registered: ‎08-14-2007

Re: Regarding xilinx blockset addsub module

Hi,

maybe you can upload the simulink model file or an VHDL export of your design.

Are you sure that the input and output busses have the correct bus width and types and the configuration of the block matches these correctly?

 

Have a nice synthesis

  Eilert

 

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