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Explorer
Explorer
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Registered: ‎02-18-2008

Relation between fpga clock and Simulink System Clock

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Hi,

 

I do not know if this query is already asked,

I have spartan3 starter kit

 

what is the relation between FPGA clock period and Simulink System Clock?

 

I try to explain my dubt:

I have a gateway in (my external ADC) with sample incoming signals at 25 Mhz; I put 10 ns in fpga clock (I'll use a dcm to generate it);

 

In Simulink System Clock I have written 10 ns ( 100 Mhz)

 

the output of ADC feed a FIR filter ( Polyphase behavior :sample in - sample out) with an hardware over-sampling rate of 4.

 

Now if I use in Simulink System Clock , instead of 10 ns , I write 1 and in the gateway in write 4 instead of 40 ns, do I get the same behaviour?

 

Thanks a lot,

AlexGiul

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Xilinx Employee
Xilinx Employee
17,574 Views
Registered: ‎08-02-2007

Re: Relation between fpga clock and Simulink System Clock

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Correct
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com

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Xilinx Employee
Xilinx Employee
15,988 Views
Registered: ‎08-02-2007

Re: Relation between fpga clock and Simulink System Clock

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To understand the relationship between the Simulink System Period and the FPGA Clock Period you first have to understand how the Simulink System Period works. 

The value you choose for the Simulink System Period in the System Generator Token block defines the overall system clock rate. For example, if the Simulink System Period is set to a value of 1 and you have gateway in blocks with a sample period of 1 then the rate these blocks will be sampled at is the same as the Simulink System Period. Another example, if the gateway in block is set to a sample period of 6, then the logic connected to that particular gateway in will be "turned on" every 6 clock cycles.  Note: You must use integer multiples of the Simulink System Period throughout your design. These integer multiples will correspond to the sample rate relative to your FPGA system clock in hardware.

 

 

RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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Explorer
Explorer
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Registered: ‎02-18-2008

Re: Relation between fpga clock and Simulink System Clock

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Thanks a lot for your answer, 

 

so you said that if I have 50 Mhz clock and I set the Simulink System clock to 1 and gateway in sample time = 1, in the hardware the port gateway in samples incoming signal at 50 Mhz,

instead if I put 2 in gateway in, the rate is half.

 

Best regards,

Alexgiul

 

 

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Xilinx Employee
Xilinx Employee
17,575 Views
Registered: ‎08-02-2007

Re: Relation between fpga clock and Simulink System Clock

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Correct
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com

View solution in original post

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Visitor
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Registered: ‎02-24-2010

Re: Relation between fpga clock and Simulink System Clock

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Is the 'FPGA clock period (ns)' field the rate at which we want the FPGA to run, or the rate at which it does run.  In other words, if we specify a desired clock rate that differs from the clock oscillator connected to the Virtex-4, will sysgen try to achieve the desired clock rate with clock dividers, etc.? 

 

After writing this I feel like the 'FPGA clock period' field can only be one value: the acutal clock rate of the hardware; but I just want to make sure.  Our FPGA runs at 192 MHz - so an appropriate entry would be (1/192e6 * 1e9).  However, we would like the design to run at 105 MHz, in order to match the rate of an ADC input we have.  If the answer to my question is what I expect, and we must put (1/192e6 * 1e9) in the FPGA clock field, are there any Xilinx blocks that can translate our 192 MHz clock to 105 MHz for universal use in the  Simulink design?

 

Thanks,

Charlie

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Visitor
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Registered: ‎11-22-2010

Re: Relation between fpga clock and Simulink System Clock

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I am interested in this question too!

 

I do not think it makes any difference here, because the sysgen does not know about the oscillator finally used. For the synthesis I generally found now difference in the design, even if I change this value to irrational numbers. But I found some problems when synthesizing for HW Cosimulation.

 

Some clarifying words would help.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Re: Relation between fpga clock and Simulink System Clock

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The value in the Field is the value at which your oscillator oscillates.


System Generator for DSP then uses this as a constraint on the design and passes it on to the implementation tools, and they will do their best to meet this constraint, when synthesizing, placing and routing the design.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Observer
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Registered: ‎03-20-2014

Re: Relation between fpga clock and Simulink System Clock

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Hello guys,

 

I have a similar question. I'm also new to  sysgen.

 

My Nexys4 (Artix-7) board has a 100Mhz oscilator.

I've set the simulink system period and all my blocks' sampling frequency to tenth of the fpga frequency above (i.e. 10Mhz or 1e-7s).

 

I've expected my board to output periodical waveforms of 20ms cycle.

This, btw, is exactly what I get in my simulink scopes.

 

Nonetheless, the actual boarrd waveforms (after being programed) viewed on a laboratory scope features 2ms period (tenth of the expected cycle). This is valid also for the sinusoidal waveform output of my DDS 6.0 module.

 

Would you exaplain what is the practical implications (if any) of the simulink system period or the sysgen block sampling frequency.

 

In addition, I've expected the above setup to devide the clock generated by the physical board oscilator to provide the desired waveforms. As this doesn't work, would you tell me how could I modify my resulting Vivado project (running ten times faster) so it would run in the desired frequency.

 

BTW, following is the header of the .xdc file generated by sysgen. As you can see a single clock is defined.

 

#######################################################################
# This file is automatically generated from System Generator for DSP  #
# design. Consult the documentation before making any modifications   #
#######################################################################
# Global Clock Constraints
create_clock -period 10.00000000000000000 -name clk [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports in_sign_ia]

...

 

Tahnks a lot, dag

 

 

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6,927 Views
Registered: ‎02-28-2011

Re: Relation between fpga clock and Simulink System Clock

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Hi dag,

 

You need to set the Simulink system period (in the Sytem Generator block) to the actual FPGA frequency. in your case "100e-6".

 

You did set it to "10e-6" and your simulation runs correctly with your settings and produces the 20ms period signal. However if you connect it to the real clock which runs at 100e-6 your hardware will run 10 times faster.

 

You simulation will runs slower with that 100e-6 clock. To get around that you can set it to 10e-6 like you have now and add a clock divder/generator in your parent project which divides the 100Mhz clock by 10.

 

Regards Markus

 

 

 

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