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Visitor revol212
Visitor
820 Views
Registered: ‎11-14-2013

SD-FEC IP simulation

I'm trying to simulate the SD-FEC IP for the Zynq Ultrascale+ RFSoC on Vivado 2018.2 but I'm not seeing any output from the IP.  Particularly, the m_axis_dout_tdata and m_axis_dout_tlast appeared invalid. 

I created the IP for 5G Encoder with everything else set to default (this doesn't matter as the issue occurred for other technology variations of the IP) with OOC option.  I then generated the example design from within Vivado.  Once the example design was created and opened, I ran Vivado simulation with the example_tb.sv file that was created.  The simulation finished but the outputs were invalid as described.  I also simulated the IP via ModelSim (DE 10.7c) (using the script in ip_user_files/sim_scripts.... and the example_tb.sv as top testbench) and got the same result.  Am I missing something or do I need to create my own testbench with my own inputs?

Screen Shot 2019-01-22 at 12.51.17 PM.png
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6 Replies
Xilinx Employee
Xilinx Employee
773 Views
Registered: ‎09-18-2018

Re: SD-FEC IP simulation

HI ,

This is know issue. Please refer to the AR : https://www.xilinx.com/support/answers/71824.html , which solves this problem.

Regards,

Vivek 

Visitor revol212
Visitor
762 Views
Registered: ‎11-14-2013

Re: SD-FEC IP simulation

I also encountered this with other standards such as Wifi or DOCSIS 3.0.  I followed the AR to generate and run it on a Linux machine.  The same problem occurred.  I think I'm missing something in generating the IP as well as the example design test bench since it's not that I got incorrect output, I got no output at all.

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Xilinx Employee
Xilinx Employee
729 Views
Registered: ‎09-18-2018

Re: SD-FEC IP simulation

Hi,

Did you apply the patch that is available in the AR for windows ?

Are you seeing the same behavior on Linux also ? IS the m_axis_data invalid ?

Can you please tell me the Vivado version you have been using ?

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Visitor revol212
Visitor
722 Views
Registered: ‎11-14-2013

Re: SD-FEC IP simulation

I didn't apply the patch as I was using Vivado 2018.2 for Windows (and the patch was 2018.3).  I did try 2018.2 as well as 2018.3 for Linux with the same result.  If possible, can you run a quick exercise on your machine starting from scratch to see if you get the same result (creating project, then IP, then open example design and run the simulation)?  I'm trying to see if I'm missing something.

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Xilinx Employee
Xilinx Employee
708 Views
Registered: ‎09-18-2018

Re: SD-FEC IP simulation

Hi ,

I see that there is a similar issue which has been reported internally for a case LDPC code has been used and example test bench has been generated. I will follow that and update you based on that.

 

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Visitor tuvanlap
Visitor
360 Views
Registered: ‎05-31-2018

Re: SD-FEC IP simulation

I meet the same problem. I updated patch AR71874. LDPC encoder example testbench run OK but  LDPC decoder example testbench, the m_axis_dout_tdata and m_axis_dout_tlast appeared invalid

Capture_decoder.JPG
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