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dgurgunoglu
Visitor
Visitor
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Registered: ‎02-24-2020

SD-FEC Issues in 5G LDPC decoder mode (Vivado 2018.3 + ZCU111 RFSoC Board)

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Hello,

I am experiencing some trouble working with SD-FEC IP in 5G mode (LDPC decoding). After decoding 12 blocks, the IP stops working. I attached a screenshot of the simulation. I am reading from m_axis_status interface, and interrupt remains low, i.e., no problem with s_axis_din_tlast signaling. The control parameters are configured as follows:

- max_schedule : 0
- mb : 46
- term_on_no_change: 1
- term_on_pass: 1
- include_parity_op: 0
- hard_op: 1
- sc_idx: 13
- bg: 0
- z_set: 1
- z_j: 7

So the decoder takes 26112 LLR values (I feed the first 768 LLR values as zero, since that is the systematic part of the codeword, which was also removed at the transmitter side), and read 8448 bits of output. s_axis_din interface takes 8 LLR's per clock, and yields 128 bits per clock at the output. I am feeding the same codeword over and over again for verification, however, the IP stops working after 12 decoding cycles. I also read the 'pass' bit from the status output as 1, and I know the uncoded version of my input, i.e., the output is correct at m_axis_dout interface. The only problem is that after decoding 12 codewords, the IP stops working. What might be the problem here?

xilForum_sdfec.PNG
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vkanchan
Xilinx Employee
Xilinx Employee
351 Views
Registered: ‎09-18-2018

Hi @dgurgunoglu ,

Every DIN data input block  to the core must be preceded with a control word and DIN_Words data. In the above waveform, the CTRL tvalid signal is high only initially and later it is always low.

Can you confirm if a valid control word is specified for each DIN input data block ? If not, please provide a valid control word to the core to act on the DIN tdata.

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vkanchan
Xilinx Employee
Xilinx Employee
352 Views
Registered: ‎09-18-2018

Hi @dgurgunoglu ,

Every DIN data input block  to the core must be preceded with a control word and DIN_Words data. In the above waveform, the CTRL tvalid signal is high only initially and later it is always low.

Can you confirm if a valid control word is specified for each DIN input data block ? If not, please provide a valid control word to the core to act on the DIN tdata.

View solution in original post

dgurgunoglu
Visitor
Visitor
336 Views
Registered: ‎02-24-2020

Hi @vkanchan , it worked, thanks a lot! I counted exactly 12 cycles of valid control words in my previous configuration, so that is why it only decodes 12 blocks. Now I converted it to continuous mode, so now it continuously decodes words.

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