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Visitor tkolcak
Visitor
637 Views
Registered: ‎09-21-2018

SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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Hello,

I am observing some issues with the output signals of the SD-FEC core both in simulation and on hardware (ZCU111 RFSoC board).

SD-FEC core configuration parameters are:

  • 5G LDPC Encode mode
  • Initialized S_AXI interface
  • Interrupts (including ECC) enabled
  • DIN and DOUT to be preconfigured interfaces (1 lane, fixed word configuration and 16 as number of words)

sdfec-1.jpg

sdfec-2.jpg

Attached are some screenshots of the simulation. This simplified testbench design consists of a single FIFO with AXI-Stream interfaces feeding data to the SD-FEC core and SD-FEC configured as above.

  • All SD-FEC clocks (including core_clk) are tied to same clock source.
  • SD-FEC CTRL world is supplied for each input data block for one clock cycle. The only difference between successive CTRL words is the 'packet id' field (bits 31 downto 24) which is incremented by 1 for each input data block.
  • The other CTRL word parameters are fixed to below values
    max_schedule: 0
    mb: 46
    z_set: 1
    z_j: 7
    bg: 0
  • For each data input block to be encoded, tlast is supplied at the last sample of the block. The interrupt output of the SD-FEC core is all clear with no tlast problems asserted during simulation.sdfec-3.jpg

     

    sdfec-4.jpg

Issues observed:
- SD-FEC core stops producing output data after 22 blocks (data and CTRL word for 23rd block is consumed but no output).
- STATUS output (which should be same as CTRL input) does not change.

First issue (core stopping to run after 22 blocks) is very critical and there is no workaround I can think of. Both issues occur in simulation and on hardware (hardware design is a larger design using DMA to access SD-FEC core, but with the same problems occurring during execution).

Any help on resolving these issues is very much appreciated.

Thanks

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Moderator
Moderator
553 Views
Registered: ‎08-01-2007

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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The buffers on the interfaces that allow a small amount of data to be input on DIN and DOUT_WORDs does not mean the users can randomly send their tlast.

The tlast is just checked to generate an interrupt. So this should not the root cause.

Can you connect m_axis_status_tready to 1? It's tied to 0, which might be the root cause.

5 Replies
Moderator
Moderator
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Registered: ‎08-01-2007

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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I do not see obvious issue with your SDFEC IP settings, except the tlast on the 23rd block. Can you make sure tlast is asserted at the last sample of 23rd block?

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Visitor tkolcak
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Registered: ‎09-21-2018

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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Hi nathanx,

Thanks for your reply.

I think the reason for tlast appearing before the end of data blocks (not only for 23rd block, but actually for all blocks) is that SDFEC core operates with a shallow buffer on input before reading CTRL input (in other words, SDFEC core continue reading a portion of next input data block after tlast).

Per PG256 page 53
"Also, as shown in the following figure, there are shallow buffers on the interfaces that allow a small amount of data to be input on DIN and DOUT_WORDS before
associated block control is provided on CTRL. This data is not processed by the SD-FEC core until the latter is available."

SDFEC core also asserts interrupt when tlast is missing or unexcpected on the input interface (PG256, page 51). For the simulation above, you can see interrupt line is clear (no tlast problems). When I make tlast asserted as you advised, I still can not get the 23rd block and I see interrupt line is now asserted reporting a tlast issue.

https://www.xilinx.com/support/documentation/ip_documentation/sd_fec/v1_1/pg256-sdfec-integrated-block.pdf

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Moderator
Moderator
554 Views
Registered: ‎08-01-2007

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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The buffers on the interfaces that allow a small amount of data to be input on DIN and DOUT_WORDs does not mean the users can randomly send their tlast.

The tlast is just checked to generate an interrupt. So this should not the root cause.

Can you connect m_axis_status_tready to 1? It's tied to 0, which might be the root cause.

Visitor tkolcak
Visitor
537 Views
Registered: ‎09-21-2018

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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Yes ! When m_axis_status_tready is set to 1, I can get the encoded output of the 23rd and successive blocks. I know CTRL can be used to control output but it looks like STATUS should also be kept being read to get output all time.

I didn't see anything related to this behaviour in SDFEC documentation.

Thanks and kudos !

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Moderator
Moderator
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Registered: ‎08-01-2007

回复: SD-FEC issues in 5G mode (Vivado 2018.3 + ZCU111 RFSoC board)

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As you have already know, all the SDFEC interfaces have a small buffer to store inputs/outputs. This is also the same for m_axis_status interface, if the user does not read data from this interface, the small fifo of m_axis_status will be full, which will then stops the core working.

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