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2,314 Views
Registered: ‎02-27-2013

SIMULATION ERROR

HELLO SIR...

i am new to xilinx simulink finding so many troble while executing design recently i had design 3tap iir filter and i need to give one sample has a input at every clock period when i am giving input from workspace than looking output from scope is correct and when i am giving dsp discreate sine wave i ma gattine single line.can u suggest me why i am geeting wrong output and single line .......i am sending screen sort of both input and result of both input..........please help me i my collge no one familar with ths tool

 

 

 

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Xilinx Employee
Xilinx Employee
2,308 Views
Registered: ‎08-02-2011

Re: SIMULATION ERROR

Probe the output of the 'Gateway In' and see what your data looks like after being passed through the 'Gateway In'

How are you setting the options in the 'Sine' block and the 'Gateway In' block. Be careful about binary point setting and Sine wave amplitude
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