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Visitor emack
Visitor
9,145 Views
Registered: ‎05-11-2015

[SYSGEN] Very slow HW Cosimulation

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Hello to everyone, this is my first post here. I'm new to FPGA programming and to System Generator for DSP, even though I've already followed the introductive lessons in UG948 tutorial. 

 

Here is my question: when I would like to multiply two matrices (put, 1920 * 1080 frames for example), or make a simple elementwise arithmetic operation between two large arrays, my HW Cosimulation is very slow. 

 

dsp00.PNG

 

Ts is 1 sample/sec, according to Simulink Sample Time. Here is my System Generator Clock setting:

 

dsp03.PNG

 

Here is the Simulation report:

dsp01.PNG


But, when I come to JTAG HW Cosimulation, the elapsed time increases a lot:

dsp02.PNG

 

I'm using MATLAB R2014a and Vivado 2014.4. My board is a Zynq ZC706 Evaluation Kit. 

Any help or hint is welcome. I'm trying to use FIFOs now, in order to increase runtime speed. 

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Teacher eilert
Teacher
15,988 Views
Registered: ‎08-14-2007

Re: [SYSGEN] Very slow HW Cosimulation

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Hi,

that is a normal observation when using such small blocks.

The slow interface and I/O scheduling betwen host and FPGA target cause this effect.

 

For your example try to imagine how fast the computer can move the data between memory and FPU, since you are doing just a simple multiplication.

 

The situation will change if you are going to HW-Cosimulate some really complex algorithm.

I posted a forum thread about this topic some time ago.

      http://forums.xilinx.com/t5/DSP-Tools/HW-cosimulation-speed-with-ml506/m-p/184408#M4618

Only if the computation of the next output event takes longer than the I/O exchange the HW-Cosimulation saves you some time.

 

 

Have a nice simulation

  Eilert

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6 Replies
Teacher eilert
Teacher
15,989 Views
Registered: ‎08-14-2007

Re: [SYSGEN] Very slow HW Cosimulation

Jump to solution

Hi,

that is a normal observation when using such small blocks.

The slow interface and I/O scheduling betwen host and FPGA target cause this effect.

 

For your example try to imagine how fast the computer can move the data between memory and FPU, since you are doing just a simple multiplication.

 

The situation will change if you are going to HW-Cosimulate some really complex algorithm.

I posted a forum thread about this topic some time ago.

      http://forums.xilinx.com/t5/DSP-Tools/HW-cosimulation-speed-with-ml506/m-p/184408#M4618

Only if the computation of the next output event takes longer than the I/O exchange the HW-Cosimulation saves you some time.

 

 

Have a nice simulation

  Eilert

View solution in original post

Visitor emack
Visitor
9,100 Views
Registered: ‎05-11-2015

Re: [SYSGEN] Very slow HW Cosimulation

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Thank you for your answer. So, JTAG is unfit for high data rates. My next question is: which is the best cosimulation setting for video processing?

 

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Teacher eilert
Teacher
9,079 Views
Registered: ‎08-14-2007

Re: [SYSGEN] Very slow HW Cosimulation

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Hi,

HW-cosimulation is not intended to provide any specified (high) datarate.

That's because the interface between simulation host and FPGA has to be synchronized to handle I/O events.

The interface can be lightning fast, but if the simulation host needs some time to calculate the next input event, this is the limiting factor. And in complex simulations this is not a rare condition even with the (slow) JTAG interface.

 

There is the option to use HW-Cosimulation in the free-running mode.

There you have no such event synchronisation, but also no real simulation control.

Still you can exchange some status information and observe how this affects the behavior of your circuit.

 

In your case this would mean, that you feed your picture data e.g. via some hdmi input from a PC or camera and output the result to a monitor, while your simulation host PC controls the settings of your cores, e.g. gamma value for gamma correction.

 

However, this requires that you also implement the full interfaces needed for the video I/O.

 

Have a nice simulation

   Eilert

 

 

Visitor emack
Visitor
9,077 Views
Registered: ‎05-11-2015

Re: [SYSGEN] Very slow HW Cosimulation

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Again. Many thanks!
So, in Simulink, I have to implement the interfaces needed for the video I/O, right?

At this point, It should be more convenient to implement the design and verify it outside the Simulink environment, right?
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Teacher eilert
Teacher
9,071 Views
Registered: ‎08-14-2007

Re: [SYSGEN] Very slow HW Cosimulation

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Hi,

while it's not easy, you can implement the interfaces with sysgen (xilinx blockset)  using simulink.

If you are doing it that way the Black Box symbol to include HDL sources or special IP-Cores will be quite helpful.

 

FPGAs are most versatile, so every predefined environment will only be useful for a limited number of people.

But even if somone would offer a solution that suits your special needs it would be quite expensive. (Of course, the saved working time for the local engineer and faster time to market might compensate the price for a company that develops a commercial application.)

 

 

e.g. National Instruments offers some "Plug and play" environment. And it might indeed offer a high turnaround time during the test and implementation phase. But probably no Matlab/Simulink connection and wether it is usable for video applications needs to be checked carefully.

 

Have a nice simulation

  Eilert

 

Visitor emack
Visitor
9,011 Views
Registered: ‎05-11-2015

Re: [SYSGEN] Very slow HW Cosimulation

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Thank you for your precious advices. :-)
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