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Explorer
Explorer
653 Views
Registered: ‎10-16-2018

Selecting Filter Architecture

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Hi ,

I am using a signal of a frequency of 16 kHz sinewave, and the sampling frequency (Fs) is 48 kHz in my design, and I want to test  it with FIR filter compiler 7.2. 

I built simple design (first attached picture), consists form a DDS compiler and FIR compiler. Then I imported the FIR coeffiecents from Tfilter tool. However, the FIR filter was passing even the frequncies in the stopband, as illustrated in this discussion thread.

I looked through UG073, and I found figure 5.1 (second attached picture) shows the sampling frequcies lower than 0.5 MHz is processed by Sequnctial FIR filter architechure. While the FIR compiler options are only providing Parallel FIR filter architecure (Systolic Multiply Accumulate)  as shown in the third attached picture.

Is there any way to change the filter architecture in FIR compiler 7.2 ?

If only this architechture (Systolic) is available, what I can do to stop the frequencies in the stopband from passing the FIR filter?

Thanks.

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TheDesign.JPG
Selecting Filter Architecture.JPG
Systolic.JPG
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1 Solution

Accepted Solutions
470 Views
Registered: ‎06-21-2017

Re: Selecting Filter Architecture

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Latency isn't the issue, throughput is.  It doesn't matter how many clock cycles the filter requires to produce an output.  What matters is how many clock cycles must pass before you can enter a new sample into the filter.  The two concepts are different.  You must set the sampling frequency equal to or higher than the rate you are entering data into the filter.  In genreal, the higher the sampling frequency, the greater the resource utilization given the same system clock frequency.  If you generate a filter with a sampling frequency of 50 KHz, don't enter data at an average rate any higher than 50KHz.  If you see that you are trying to enter data faster than your filter can accept it, based on tready and tvalid, you will not get good results.  You will need to either create a filter with a higher sampling frequency or reduce the rate tvalid is trying to clock data into your filter.

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7 Replies
Xilinx Employee
Xilinx Employee
575 Views
Registered: ‎06-13-2018

Re: Selecting Filter Architecture

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Hello @ahmed_alfadhel,

 I looked through UG073, and I found figure 5.1 (second attached picture) shows the sampling frequcies lower than 0.5 MHz is processed by Sequnctial FIR filter architechure

I believe this is not a case. I am able to use this at the 100MHz of sampling frequency. Can you please share the following details with us:

1. What is your input sampling frequency?

2. How you are calculating the FIR coefficient? 

3. Please share the screenshot of your output waveform.

4. If possible please share the complete project with us. If no, please share the complete set up of both the FIR filter and the DDS IP.

5. Form your attached picture, its looks like that you are selecting the Sine and cosine option in your DDS IP as an output. Please select it as sine and then try to run the design.

Regards,

Naveen 

 

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Explorer
Explorer
540 Views
Registered: ‎10-16-2018

Re: Selecting Filter Architecture

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Hi @nmanitri ,

Accorrding to your requenst:

1. Fs = 50 kHz.

2. I am using TFilter tool to indicate the filter coeffecients. As follow:

stopband1 : 0 to 15.5 kHz , ripple/att. = -40 dB.

Passband : 16 kHz to 17 kHz , ripple/att. = 5 dB.

stopband2 : 17.5 kHz to 24 kHz ripple/att. = -40 dB.

3. The screenshot for output waveform is attached below:24kHz_Fs50kHz.JPG24 kHz passed !

4. I uploaded the project as a RAR file in my Google Drive. Sharable link.

5. I run simulation for DDS with "sine output only" . There is no difference from the case of "sine & cosine output".

Thanks, I am looking forward your reply.

 

 

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Registered: ‎06-21-2017

Re: Selecting Filter Architecture

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Your valid signal is always high.  Your ready signal is toggling.  You are trying to put data into the filter when it is not ready and it is dropping samples.  This creates the harmonics you are seeing.

Explorer
Explorer
503 Views
Registered: ‎10-16-2018

Re: Selecting Filter Architecture

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Hi @bruce_karaffa ,

Thank you for your reply. You are leading me to understand how each IP core is communicating with the other. 

I looked through the manuals of DDS (PG141) and FIR (PG149) , and I deduced that I need to control the "Latency Cycles", in order in conrol the TREADY signal comming from FIR filter.

Could you please tell me how to control the "Latency Cycles" ?

Kindly, see the attached picture (summary of FIR settings).

Thanks, 

cycle_latency.JPG
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471 Views
Registered: ‎06-21-2017

Re: Selecting Filter Architecture

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Latency isn't the issue, throughput is.  It doesn't matter how many clock cycles the filter requires to produce an output.  What matters is how many clock cycles must pass before you can enter a new sample into the filter.  The two concepts are different.  You must set the sampling frequency equal to or higher than the rate you are entering data into the filter.  In genreal, the higher the sampling frequency, the greater the resource utilization given the same system clock frequency.  If you generate a filter with a sampling frequency of 50 KHz, don't enter data at an average rate any higher than 50KHz.  If you see that you are trying to enter data faster than your filter can accept it, based on tready and tvalid, you will not get good results.  You will need to either create a filter with a higher sampling frequency or reduce the rate tvalid is trying to clock data into your filter.

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Xilinx Employee
Xilinx Employee
460 Views
Registered: ‎06-13-2018

Re: Selecting Filter Architecture

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Hello @ahmed_alfadhel,

As @bruce_karaffa has mentioned "It doesn't matter how many clock cycles the filter requires to produce an output.  What matters is how many clock cycles must pass before you can enter a new sample into the filter. " The design which you has been shared with us, it seems that your input sampling frequency is 0.001MHz and your DDS output frequency is 0.024 MHz, that's the reason you are not getting a good result. You must set the sampling frequency equal to or higher than the rate you are entering data into the filter. I changed your DDS output frequency and I am getting the correct result.

Regards,

Naveen 

 

Explorer
Explorer
438 Views
Registered: ‎10-16-2018

Re: Selecting Filter Architecture

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@bruce_karaffa wrote:

  You must set the sampling frequency equal to or higher than the rate you are entering data into the filter.



Thank you @bruce_karaffa  for perfect analyzing . Thank you @nmanitri  for your follow up. 

I will keep using the system clock (sys_clock) of 200 MHz and I will try to clock the FIR filter with low clock ,like 200 kHz (with the aid of counter) , and I will make Fs also equal to 200 kHz .

I think this will work.

Thanks.

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