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Participant
Participant
9,301 Views
Registered: ‎10-16-2010

Semantic error in Divider

Hello, I´m looking for a divider to use in System Generator.

How can get 1/1 = 1?

Thank you for your help!ErrorinDividerblock.JPG

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Xilinx Employee
Xilinx Employee
9,290 Views
Registered: ‎05-23-2008

Hi

are the inputs set up correctly.

what are the gateway inpoust set up to

 

regards

Mike

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Participant
Participant
9,286 Views
Registered: ‎10-16-2010

Well, that´s part of my question, I don´t know how I should set up the input and output blocks correctly.

I´ve put it (and the Cordic Divider Block) as unsigned but I don´t get the proper result.

 

 

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Xilinx Employee
Xilinx Employee
9,227 Views
Registered: ‎11-28-2007

You just need to run the simulation longer. Note the "Z-31" on the Cordic block, which indicates the latency of the block is 31 clock cycles, so the simulation needs to longer than that to see the valid output. If you change the sim time from 10 to 100, you will see the correct result.

 


@2010stone wrote:

Hello, I´m looking for a divider to use in System Generator.

How can get 1/1 = 1?

Thank you for your help!ErrorinDividerblock.JPG


 

Cheers,
Jim
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Participant
Participant
9,218 Views
Registered: ‎10-16-2010

I´ve gotten to do 1/1 = 1. The parameter configuration for the CORDIC blocks is 

Number of Processing Elements:1

Data Widht:16

Binary Point Position:14

Latency for each Processing Element [001]: default

 

The parameters for the two Gateway in blocks are:

Output type: Unsigned

Number of bits: 16

Binary point: 14

 

Thank you for your response but it  should be contain some error...

See the picture below, the latency of the Cordic Block is 21 and the sim time is 10. So is apparenty is incorrec to afirm that the sim time it has to be higher than the latency of the block to get the proper output result.CordicDivider.LatencyandSimTime.JPG

Thank you for your attention.

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Xilinx Employee
Xilinx Employee
9,215 Views
Registered: ‎11-28-2007

It may work for 1/1, but may not work for all input values. As an exercise for you: try change y inpt to 0.5 and see what you get. The point I'm trying to make is that if the latency of the block is 21, you may get the "right" result earlier, but that's not a valid result. You may also want to read about how CORDIC works before using the CORDIC divider.

Cheers,
Jim
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Xilinx Employee
Xilinx Employee
9,211 Views
Registered: ‎08-01-2007

You can also use the divider generator.
Chris
Versal ACAP: AI Engines | Embedded SW Support

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Participant
Participant
9,184 Views
Registered: ‎10-16-2010

I´m using the  System Generator of the 9.2.01 version of ISE. Does this version contain Divider Generator?

Thank you.

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Xilinx Employee
Xilinx Employee
9,113 Views
Registered: ‎08-01-2007

The divider wasn't added until the 10.x time frame.
Chris
Versal ACAP: AI Engines | Embedded SW Support

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Participant
Participant
9,038 Views
Registered: ‎10-16-2010

Well, I get 1/1 = 1. The parameters configuration are:

Number of Processing Elements: 1

X,Y Data Width: 16

X, Y, Binary Point Position: 14

Latency for each Processing Element [001]:

[1 1 1 1 1 1 1 1 1 1 1 ]

 

But now, I don´t get 0.1/0.2 = 0.5

What can I do it?

Thank you for your help.

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Xilinx Employee
Xilinx Employee
2,966 Views
Registered: ‎11-28-2007

Let me say this for the third time (and last time): go back to your orignal model (which is attached to your first message of this thread) and run simulation longer than the latency displayed for the Cordic block.

Cheers,
Jim