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Voyager
Voyager
10,237 Views
Registered: ‎05-09-2008

Serial to Parallel block problem ...

Hi,

 

have have one problem on "Serial to Parallel" problem on System generator Version 10.1.2.1250.

 

Serial ti parallel = 8 bit - Most significant word first

 

Sequenze of in       = "[0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1].'" 

Sequenze of enable = "[0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1].'"

 

This is a model:

 

Serial to Parallel Model
 And this is the simulation of mode:

 

 Serial to Parallel scope

 

Someone can explain why not working ?

 

For every "Enable" should enable the shift reg, but they are wrong !

 

It seems that the schift reg is always active, and catching only when enable goes up. Why ?

 

It should enable the shift reg with enavle high ?

 

Someone has the same problem ?

 

Thanks.

 

Kappa. 

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11 Replies
Voyager
Voyager
10,210 Views
Registered: ‎05-09-2008

Re: Serial to Parallel block problem ...

Hi,

 

None of the forum has ever used this block ?
 
Please help me !!!
 
Kappa. 

 

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Xilinx Employee
Xilinx Employee
10,204 Views
Registered: ‎09-28-2007

Re: Serial to Parallel block problem ...

The output of the serial-to-parallel block looks correct.  dout outputs 1 sample for every 8 samples of din . Out of the 8 din samples, only 4 samples (with the pattern of 0 1 0 1) are actually pushed into the shift register due to the enable signal.

      s2p din : 0 0 0 1 0 0 0 1 / 0 0 0 1 0 0 0 1 / 0 0 0 1 0 0 0 1 / 0 0 0 1 0 0 0 1
   s2p enable : 0 1 0 1 0 1 0 1 / 0 1 0 1 0 1 0 1 / 0 1 0 1 0 1 0 1 / 0 1 0 1 0 1 0 1
     shift in :   0   1   0   1 /   0   1   0   1 /   0   1   0   1 /   0   1   0   1
shreg content :            0x05 /            0x55 /            0x55 /
     s2p dout : 0x00            / 0x05            / 0x55            / 0x55
 

 

Initially, the shift register holds 00000000 (0x00). 0101 is pushed into the shift register for the first 8 samples. The shift register then outputs 00000101 (0x05). Another 0101 is pushed into the shift register for the second 8 samples. From that moment, the shift register holds and outputs 01010101 (0x55).

 

What is your expected waveform? You may want to use the enable signal and sample period differently to implement what you need.

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Voyager
Voyager
10,198 Views
Registered: ‎05-09-2008

Re: Serial to Parallel block problem ...

Hi benchan, thanks for you replay.

 

Your analysis is very precise, I would not have been able to do better.

 


Initially, the shift register holds 00000000 (0x00) ...


OK I agree.

 


... 0101 is pushed into the shift register for the first 8 samples. The shift register then outputs 00000101 (0x05). Another 0101 is pushed into the shift register for the second 8 samples. From that moment, the shift register holds and outputs 01010101 (0x55).


Why ? The shift register should be active only with enable high !!!

 

Enable refers only to the data input, while the shift register continues to rotate ?
 
If I had to stop the shift reg for some reason like I do ? 
 
Thanks.
 
Kappa.
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Xilinx Employee
Xilinx Employee
10,195 Views
Registered: ‎09-28-2007

Re: Serial to Parallel block problem ...

Yes, the shift register is active (i.e. shift in one din sample) only when the s2p enable is high. But the s2p block is a rate changing block, so there are two clock enable signals to consider, one for din and one for dout. And note that the dout register reacts only to the clock enable, not the s2p enable signal. 

 

Assuming the normalized periods of clock enable are 1 and 8 for din and dout, respectively. The following diagram may illustrate better how the shift register and output register react to the s2p enable and clock enable signal.

 

(I don't know how to attach a picture, so bear with my ASCII drawing again.)

 

       shift                                        dout
cycle  enable  din        shift register content    register  dout
                                                    enable
---------------------------------------------------------------------
                         LSB                  MSB
 0:     0       0         0  0  0  0  0  0  0  0      0       0x00
 1:     1 -->  [0] -->   [0] 0  0  0  0  0  0  0      0
 2:     0       0         0  0  0  0  0  0  0  0      0
 3:     1 -->  [1] -->   [1  0] 0  0  0  0  0  0      0
 4:     0       0         1  0  0  0  0  0  0  0      0
 5:     1 -->  [0] -->   [0  1  0] 0  0  0  0  0      0
 6:     0       0         0  1  0  0  0  0  0  0      0
 7:     1 -->  [1] -->   [1  0  1  0] 0  0  0  0  <== 1
 8:     0       0         1  0  1  0  0  0  0  0      0       0x05
 9:     1 -->  <0> -->   <0>[1  0  1  0] 0  0  0      0
10:     0       0         0  1  0  1  0  0  0  0      0
11:     1 -->  <1> -->   <1  0>[1  0  1  0] 0  0      0
12:     0       0         1  0  1  0  1  0  0  0      0
13:     1 -->  <0> -->   <0  1  0>[1  0  1  0] 0      0
14:     0       0         0  1  0  1  0  1  0  0      0
15:     1 -->  <1> -->   <1  0  1  0>[1  0  1  0] <== 1
16:     0       0         1  0  1  0  1  0  1  0      0       0x55
17:     1 -->  (0) -->   (0)<1  0  1  0>[1  0  1]     0
18:     0       0         0  1  0  1  0  1  0  1      0
19:     1 -->  (1) -->   (1  0)<1  0  1  0>[1  0]     0
20:     0       0         1  0  1  0  1  0  1  0      0
21:     1 -->  (0) -->   (0  1  0)<1  0  1  0>[1]     0
22:     0       0         0  1  0  1  0  1  0  1      0
23:     1 -->  (1) -->   (1  0  1  0)<1  0  1  0> <== 1
24:     0       0         1  0  1  0  1  0  1  0      0       0x55

--> enable signal goes high and causes shift register to shift in one value from din.
<== output clock enable goes high and causes dout register to latch in the current shift register content. The value appears one cycle later at dout.
[]  corresponds to the first 8 din samples
<>  corresponds to the second 8 din samples
()  corresponds to the third 8 din samples

As you can see from the diagram above, the shift register shifts in a value only when enable goes high. Its content remains unchanged when enable is low. But the dout register is updated on every 8 din samples, regardless of the enable signal. So out of every 8 din samples, only 4 goes into the shift register.

 

I think you expect a different behavior. Could you draw the timing diagram to illustrate what you want to implement?

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Voyager
Voyager
10,190 Views
Registered: ‎05-09-2008

Re: Serial to Parallel block problem ...

Thanks benchan,

 

you are very precise, there is no way to be more clear.

 

I would simply dout register was linked to enable shift and not to every 8 din samples but every 8 shift enable samples. A real shift register commanded.

 

From your table amended:

 

        shift                                        dout
cycle  enable  din        shift register content    register  dout
                                                    enable
---------------------------------------------------------------------
                         LSB                  MSB
 0:     0       0         0  0  0  0  0  0  0  0      0       0x00
 1:     1 -->  [0] -->   [0] 0  0  0  0  0  0  0      0
 2:     0       0         0  0  0  0  0  0  0  0      0
 3:     1 -->  [1] -->   [1  0] 0  0  0  0  0  0      0
 4:     0       0         1  0  0  0  0  0  0  0      0
 5:     1 -->  [0] -->   [0  1  0] 0  0  0  0  0      0
 6:     0       0         0  1  0  0  0  0  0  0      0
 7:     1 -->  [1] -->   [1  0  1  0] 0  0  0  0      0

 8:     0       0         1  0  1  0  0  0  0  0      0       

 9:     1 -->  [0] -->   [0  1  0  1  0] 0  0  0      0
10:     0       0         0  1  0  1  0  0  0  0      0
11:     1 -->  [1] -->   [1  0  1  0  1  0] 0  0      0
12:     0       0         1  0  1  0  1  0  0  0      0
13:     1 -->  [0] -->   [0  1  0  1  0  1  0] 0      0
14:     0       0         0  1  0  1  0  1  0  0      0
15:     1 -->  [1] -->   [1  0  1  0  1  0  1  0] <== 1
16:     0       0         1  0  1  0  1  0  1  0      0       0x55
17:     1 -->  <0> -->   <0>[1  0  1  0  1  0  1]     0
18:     0       0         0  1  0  1  0  1  0  1      0
19:     1 -->  <1> -->   <1  0>[1  0  1  0  1  0]     0
20:     0       0         1  0  1  0  1  0  1  0      0
21:     1 -->  <0> -->   <0  1  0>[1  0  1  0  1]     0
22:     0       0         0  1  0  1  0  1  0  1      0
23:     1 -->  <1> -->   <1  0  1  0>[1  0  1  0]     0
24:     0       0         1  0  1  0  1  0  1  0      0     
25:     1 -->  <0> -->   <0  1  0  1  0>[1  0  1]     0
26:     0       0         0  1  0  1  0  1  0  1      0
27:     1 -->  <1> -->   <1  0  1  0  1  0>[1  0]     0
28:     0       0         1  0  1  0  1  0  1  0      0
29:     1 -->  <0> -->   <0  1  0  1  0  1  0>[1]     0
30:     0       0         0  1  0  1  0  1  0  1      0
31:     1 -->  <1> -->   <1  0  1  0  1  0  1  0> <== 1
32:     0       0         1  0  1  0  1  0  1  0      0       0x55  
 

--> enable signal goes high and causes shift register to shift in one value from din.
<== output clock enable goes high and causes dout register to latch in the current shift register content. The value appears one cycle later at dout.
[]  corresponds to the first  8 din samples with enable
<>  corresponds to the second 8 din samples
with enable

 

You have some idea ?

 

Thanks.

 

Kappa.

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Xilinx Employee
Xilinx Employee
10,184 Views
Registered: ‎09-28-2007

Re: Serial to Parallel block problem ...

Now I see what you want to achieve.

 

For certain fixed and simple pattern enable patterns (such as 01010101, 00010001), you can simply down sample the s2p block to approximate the behavior your described. You may or may not achieve the same dout latency depending on the enable pattern.

 

For a generic solution, you can build your own s2p circuit like this

  • use 8 1-bit register to build a shift register chain
  • connect s2p din to the din of first register in the chain; s2p enable to the enable of each register in the chain
  • concatentate the dout of all registers in the chain into a 8-bit signal; capture the 8-bit signal with a capture register
  • use the terminal count of a 3-bit free-running counter to enable the capture register; the counter is enabled by the s2p enable signal

I'm sure there are other ways to implement it. You may exploit the enable pattern to get the optimal implementation.

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Voyager
Voyager
10,172 Views
Registered: ‎05-09-2008

Re: Serial to Parallel block problem ...

Thank benchan,

 

I do not have to look for a pattern, but deserialize. Your solution is the same which I had thought. Thanks.

 

But if I were to implement a deserializzatore to 68-bit instead of 8-bit ? I will take all day just for that.
 
Be single block that not "stop" if enable is low.
 
Xilinx implements We hope that sooner or later a similar block.
 
Thanks again for your patience.
 
Kappa.
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Xilinx Employee
Xilinx Employee
10,155 Views
Registered: ‎09-28-2007

Re: Serial to Parallel block problem ...

You may find the "System Generator API for Programmatic Generation" useful for constructing a 68-bit deserializer.

 

The PG API is quite handy to create designs with repeated structures in System Generator.

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Newbie deepthi_23
Newbie
5,483 Views
Registered: ‎06-26-2013

Re: Serial to Parallel block problem ...

Hello, I'm facing a similar problem and the explanation given here doesn't seem to fit the output I'm getting. I held enable high on every 5th clock cycle and I asked for a 4 bit output. According to the logic given here, for a four bit output the d_out enable is held high on the 3rd cycle (where the value is still zero, since enable hasn't been held high even once) and on the 7th clock cycle where the value should be 8. I'm not getting a output there however.

 

In the same ascii diagram format:

 

cycle       shift enable         din                                       shift register content                                dout_enable                   dout

----------------------------------------------------------------------------------------------------------------------------------------------------------------

0:                  0                       0                                        0 0 0 0                                                                 0                                  

1:                  0                       1                                        0 0 0 0                                                                 0                                  

2:                  0                       0                                        0 0 0 0                                                                 0                                  

3:                  0                       1                                        0 0 0 0                                                                 1                                  0x0

4:                  0                       0                                        0 0 0 0                                                                 0                                  

5:                  1                       1          ---------->              1 0 0 0                                                                 0                                  

6:                  0                       0                                        1 0 0 0                                                                 0                                  

7:                  0                       1                                        1 0 0 0                                                                 1                                  0x1

 

 

The out put I see is /0 0 0 0/ 0 0 0 0/ 0 0 0 0/ 1 1 1 1.... 1 till the 20th cycle (the first value here corresponds to 0th cycle)

Can you please tell me where I am making the logical mistake?

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Newbie deepthi_23
Newbie
1,779 Views
Registered: ‎06-26-2013

Re: Serial to Parallel block problem ...

The serial to parallel block gives an output only at multiples of both the enable period and the number of bits it has to output. A formula like:

 

lcm (enable period,  (no. of bits to be output/ no. of bits input) ) should give the first clock cycle where an updated output is seen. 

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Adventurer
Adventurer
1,763 Views
Registered: ‎02-23-2013

Re: Serial to Parallel block problem ...

Hi,

 

but if I want block the shift register ? Is not possible ?

If so can not be considered a Serial to Parallel and Parallel to Serial block.

debugasm

 

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