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Visitor aklemd
Visitor
1,252 Views
Registered: ‎07-10-2017

Set VHDL-Standard for Blackbox source-files in System Generator

Hi all,

 

in Xilinx System Generator I am using a BlackBox to synthesize my VHDL-code. To have my code run I would like to have certain .vhd-files read in vhdl2008 standard. As I need unconstrained arrays in an entity port, this would simplify my code drastically.

 

In my BlackBox config m-file I add my source files such as:

this_block.addFile('src/subcomponents/addertree.vhd');
this_block.addFile('src/subcomponents/block_ram/shift_buffer.vhd');

Is there a way to have one file read in 'VHDL'93' and the other one in 'VHDL2008' standard?

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5 Replies
Xilinx Employee
Xilinx Employee
1,219 Views
Registered: ‎08-01-2008

Re: Set VHDL-Standard for Blackbox source-files in System Generator

It's not recommended to mix versions. You may synthesis design files and use netlist in place of VHDL code
Thanks and Regards
Balkrishan
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Visitor aklemd
Visitor
1,211 Views
Registered: ‎07-10-2017

Re: Set VHDL-Standard for Blackbox source-files in System Generator

Ok thank you. Then how would I set the VHDL2008 standard for all my source files?

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Xilinx Employee
Xilinx Employee
1,203 Views
Registered: ‎08-01-2008

Re: Set VHDL-Standard for Blackbox source-files in System Generator

refer chapter -6 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Visitor aklemd
Visitor
1,196 Views
Registered: ‎07-10-2017

Re: Set VHDL-Standard for Blackbox source-files in System Generator

I don't think Chapter 6 refers to how to set VHDL2008 in the system generator. I have a Xilinx BlackBox in Simulink and don't see a way to use tcl-commands in that workflow.

 

Maybe there is a Matlab-scipt command for BlackBox config .m-file? If not, I will have to implement my design without VHDL2008.

 

Thank you.

 

 

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Visitor aklemd
Visitor
1,173 Views
Registered: ‎07-10-2017

Re: Set VHDL-Standard for Blackbox source-files in System Generator

I am still having issues to use VHDL2008 in the Xilinx System Generator in MATLAB/Simulink.

 

I did not find a setting to change within the System Generator or Simulink workflow. Now I am wondering if there is a global, persisting setting for vivado to read vhdl-files using the VHDL2008 standard?

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