03-19-2018 02:22 AM
in Xilinx System Generator I am using a BlackBox to synthesize my VHDL-code. To have my code run I would like to have certain .vhd-files read in vhdl2008 standard. As I need unconstrained arrays in an entity port, this would simplify my code drastically.
In my BlackBox config m-file I add my source files such as:
Is there a way to have one file read in 'VHDL'93' and the other one in 'VHDL2008' standard?
03-20-2018 03:10 AM
03-20-2018 05:26 AM
Ok thank you. Then how would I set the VHDL2008 standard for all my source files?
03-20-2018 12:04 PM
03-21-2018 12:08 AM
I don't think Chapter 6 refers to how to set VHDL2008 in the system generator. I have a Xilinx BlackBox in Simulink and don't see a way to use tcl-commands in that workflow.
Maybe there is a Matlab-scipt command for BlackBox config .m-file? If not, I will have to implement my design without VHDL2008.
04-02-2018 11:28 PM
I am still having issues to use VHDL2008 in the Xilinx System Generator in MATLAB/Simulink.
I did not find a setting to change within the System Generator or Simulink workflow. Now I am wondering if there is a global, persisting setting for vivado to read vhdl-files using the VHDL2008 standard?