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Newbie
Newbie
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Registered: ‎08-05-2020

Shared Memory in System Generator 2020.1

Hi,

I am trying to migrate a design from SysGen 14.7 to SysGen 2020.1 to generate an IP Core to import into Vivado's IP Integrator and then into Vitis. I am having issues migrating the Shared Memory blocks and EDK Processor as they are not available in the newest SysGen. Based on what I've found in documentation, it seems the shared memory generated by the EDK Processor block has been replaced with Gateway blocks declaring explicit AXI interfaces. So far I have been trying to replace To/From Register/FIFO blocks with Gateway In/Out blocks and setting the Implementation to AXI4-Lite. Is this the recommended approach for migrating System Generator designs with the EDK Processor block or is there an alternative method?

Thanks for the help!

Alex

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Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎09-18-2018

A link to UG897 older version is provided below and Appendix B contains guidelines to migrate design from ISE to Vivado.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug897-vivado-sysgen-user.pdf

 

However for the EDK block and shared memory blocks the following steps have to be followed additionally.

 

EDK processor : Since this block is no longer supported in the Vivado release of Sysgen, the corresponding design blocks to which it is interfaced should be exported as IP catalog in Vivado’s Sysgen. The control interfaces should have AXI-lite interfaces and data interface should be of AXI-stream interface type. Then the IP can be interfaced to processor in the Vivado IP integrator tool.

 

Shared Memories : These were used for Multi clock domain designs in the design. In that case, the guidelines in the section “Migrating Multiple-Clock ISE Designs into the Vivado IDE” have to be followed to replace these blocks.

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