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Observer mafgani
Observer
7,735 Views
Registered: ‎05-06-2009

Shared memory simulation

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Hi,

 

is it possible to run software simulations of shared memory blocks before compiling them for hardware co-simulation? They seem to work fine when compiled and run on an FPGA but I run into the following error when trying software simulations of the shared memory subsystem:

Error reported by S-function 'xltoshmem' in 'shm_test/Shared Memory Write':

-- The Shared Memory Write block could not obtain a lock for the specified shared memory.

 

The reason I am asking is to quickly debug some additional logic that goes together with the shared memory on the hardware side ...

 

Thanks.

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Xilinx Employee
Xilinx Employee
8,803 Views
Registered: ‎09-28-2007

Re: Shared memory simulation

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For software only simulation, you can simply use the regular shared memory blocks (those in blue color): Shared Memory, From Register, To Register, From FIFO, To FIFO.

 

A To FIFO and a From FIFO with the same shared memory name can work together as a full FIFO. To FIFO is the write side and the From FIFO is the read side. Suppose your design takes data from a From FIFO. You can construct a test-bench that produces data to your design via a To FIFO. The test-bench and the design can be in the same Simulink model or in separate Simulink models. The To  and From FIFO are scheduled based on their respective sample period (unlike the Shared Memory Read and Write block that uses frame-based transfer).  Shared Memory, and To/From Register work in a similar fashion.

 

System Generator user guide has a chapter called "Frame-Based Acceleration using Hardware Co-Simulation", which describes how to use the regular shared memory blocks to in a software simulation, and then migrate the design to a frame-based simulation using the Shared Memory Read and Write block.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/sysgen_user.pdf

 

This application note (XAPP1031) provides a more in-depth explanation and analysis of the shared memory mechanism.

http://www.xilinx.com/support/documentation/application_notes/xapp1031.pdf 

 

6 Replies
Xilinx Employee
Xilinx Employee
7,710 Views
Registered: ‎08-16-2007

Re: Shared memory simulation

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Make sure your Shared Write's and Shared Reads in your model have the same names as the Shared Memory Blocks.
What version of SysGen are you using?

Make sure your Shared Write's and Shared Reads in your model have the same names as the Shared Memory Blocks.
What version of SysGen are you using?

 

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Observer mafgani
Observer
7,702 Views
Registered: ‎05-06-2009

Re: Shared memory simulation

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Hi criley23, as I've mentioned, the design runs fine in hardware so it isn't a problem with naming the shared memory. I just wanted to see if I could simulated the shared memory subsystem in software (i.e. simulink) before compiling it into a hardware co-sim block. I am using SysGen 12.2. Thanks.
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Xilinx Employee
Xilinx Employee
7,682 Views
Registered: ‎09-28-2007

Re: Shared memory simulation

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To answer your question, we need to first explain the usage of different types of shared memory blocks. There are two types of blocks in the Shared Memory library:

 

1. Those in blue color: Shared Memory, From Register, To Register, From FIFO, To FIFO

 

These blocks are used to construct a design, i.e. both simulatable and synthesizable. Like other blocks in the System Generator library, they are simulated on a cycle basis per Simulink sample period and consume/produce one data word per sample period

 

2. Those in yellow color: Shared Memory Write, Shared Memory Read 

 

These are simulation-only special blocks that are used to bolster simulation performance by utilizing frame-based transfers. They write or read data of multiple cycles to the corresponding shared memory pair (the blue ones) per Simulink sample period. Thus, they are normally used with hardware co-simulation in free-running mode.

 

There are a mismatch of data consumption / production rate when mixing these two types of block, which may result in unexpected simulation semantics. The rate mismatch may be rectified by using the Simulink Enabled Subsystem to effectively sample the Shared Memory Read / Write block for every N sample period, where N is greater than or equal to the frame size. However, you still need to follow the Lockable Shared Memory protocol that the Shared Memory Read / Write block expects. This is the issue that you have run into. You can find the description of Lockable Shared Memory in the System Generator user guide.  Nevertheless, even if you can mix these two types of shared memory block in a simulation, you may see a different simulation behavior when running a hardware co-simulation in free-running mode.

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Observer mafgani
Observer
7,673 Views
Registered: ‎05-06-2009

Re: Shared memory simulation

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Hi benchan, thanks for the explanation. I understand why my (software) simulations failed to run with the shared memory read/write blocks. Which now brings me to my next question: if I can't used the shared memory read/write blocks in a software-only simulation, how can I simulate a software only design containing a shared memory block? Many thanks for your help.
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Xilinx Employee
Xilinx Employee
8,804 Views
Registered: ‎09-28-2007

Re: Shared memory simulation

Jump to solution

For software only simulation, you can simply use the regular shared memory blocks (those in blue color): Shared Memory, From Register, To Register, From FIFO, To FIFO.

 

A To FIFO and a From FIFO with the same shared memory name can work together as a full FIFO. To FIFO is the write side and the From FIFO is the read side. Suppose your design takes data from a From FIFO. You can construct a test-bench that produces data to your design via a To FIFO. The test-bench and the design can be in the same Simulink model or in separate Simulink models. The To  and From FIFO are scheduled based on their respective sample period (unlike the Shared Memory Read and Write block that uses frame-based transfer).  Shared Memory, and To/From Register work in a similar fashion.

 

System Generator user guide has a chapter called "Frame-Based Acceleration using Hardware Co-Simulation", which describes how to use the regular shared memory blocks to in a software simulation, and then migrate the design to a frame-based simulation using the Shared Memory Read and Write block.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/sysgen_user.pdf

 

This application note (XAPP1031) provides a more in-depth explanation and analysis of the shared memory mechanism.

http://www.xilinx.com/support/documentation/application_notes/xapp1031.pdf 

 

Observer mafgani
Observer
7,626 Views
Registered: ‎05-06-2009

Re: Shared memory simulation

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Ah! I did read all of that but failed to realise (until now) that I could simply use a second shared memory block of the same name to simulate a shared memory based buffer subsystem. Thanks for you help!
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