02-28-2018 04:57 AM
I am simulating the test bench for the IP DPD v8.1 in Vivado 2017.2.
The 'DPD Host Process' is never executed because the variable 'start_demo' never changes from the value 0. This variable is updated in the 'DPD CTRL Interfacing process (AXI4-Lite)'.
In the simulation window all the output signals of the core are marked with 'U'.
Has anyone simulated this test bench that can help me solve this problem?
03-05-2018 08:36 PM
DPD IP core provide demonstration Test Bench When the core is generated using the Vivado IDE, a demonstration test bench can be created
This is a simple VHDL test bench that exercises the core. The demonstration test bench source code is one VHDL file: demo_tb/tb_.vhd in the Vivado output directory.
The test bench is intended to show the DPD command shell handshake process between user interface and control interface.
In addition to this the test bench shows behavior of clocks and reset along with behavior of the core
The detail information on the demonstration test bench is available in the tb_readme.txt file that is generated as part of the test bench
03-06-2018 01:15 AM
Thanks for your reply.
The file tb_readme.txt is not created when I generate the test bench. I can't find tis file in the Vivado output directory.
I have problems with the test bench simulation in Vivado because all the output signal of the core are marqued whit then symbol 'U'. The simulating time is 50 us.
The tb_readme.txt file is not created when I build the test bench. I can not find this file in the Vivado output directory.
I have any kind of problem with the simulation of the test bench in Vivado because all the output signals from the core are marked with the 'U' symbol. The simulation time is 50 us, and the signal 'start_demo' never changes from the value '0', because the process that handles that signal is waiting for the signal s_axis_ctrl_wready to change to the value '1', and this event never happens.