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Registered: ‎09-26-2007

Simulation model of Multiply-Accumulator V4.0

  I have been trying to use the Multiply Accumulator V4.0 IP. I encountered a discrepany between the behaviour specified in the datasheet and the behaviour I got when I tried to simulate the module in ModelSim. Amongst the parameters I specified the number of MAC Cycles as 4 during the module generation. The DataSheet for MAC says that such a module will take 4 data-inputs at positive clock edges when the input signal ND is asserted high and it will raise a RDY signal once the multiply-accumulate for these 4 inputs is complete. This means that I should be able to send in 4 individual data inputs in 4 consecutive clock cycles and see the sum of products after a while when RDY is asserted. But, what I observe during ModelSim simulation is that only the first product is computed when the first RDY is asserted, that only if I keep ND in a high state for 4 clock cycles for the first data input. This does not seem to be the behaviour that is described in the datasheet. Has someone encountered this problem before or have I misunderstood the datasheet. I'd appreciate any inputs regarding this.
Thank You
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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

Re: Simulation model of Multiply-Accumulator V4.0



The ND signal should be toggled for 4 cycles when RDY is active.  This means that you need to hold ND for all four input pieces of data.  Once all 4 have been received, then it can calculate 1 output.  There may be a few cycles of latency after the 4 inputs are complete.


If you see that the core is not following the Data Sheet, you may want to open a Webcase.

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