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Explorer
Explorer
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Registered: ‎10-16-2018

Simulink System Period Vs Explicit Sample Time

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Hi , 

What is the diference between Simulink System Period and Explicit Sample Time ?

Kindly , see the attached two pictures.

Also, are they affacting implementation or just affecting simulation ?

Thanks.

system_generator_simulink_period.JPG
Explicit Sample Time.JPG
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Explorer
Explorer
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Registered: ‎10-16-2018

Hi @meherp ,

Kindly see the attached picture. 

Each of pages 33, 34 in UG897 are illlustrating each of Simulink Sample Time and Sample Time

Thanks,

View solution in original post

times.JPG
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Moderator
Moderator
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Registered: ‎08-16-2018

@ahmed_alfadhel 

If you select Specify explicit sample period rather than the default, you can set the sample period required for all the block outputs. This is useful when implementing features such as feedback loops in your design. In a feedback loop, it is not possible for System Generator to determine a default sample rate, because the loop makes an input sample rate depend on a yet-to-be-determined output sample rate. System Generator under these circumstances requires you to supply a hint to establish sample periods throughout a loop.

 

See UG958 for more details. 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
Highlighted
Explorer
Explorer
590 Views
Registered: ‎10-16-2018

Hi @meherp ,

Kindly see the attached picture. 

Each of pages 33, 34 in UG897 are illlustrating each of Simulink Sample Time and Sample Time

Thanks,

View solution in original post

times.JPG
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Highlighted
Moderator
Moderator
573 Views
Registered: ‎08-16-2018

Hi @ahmed_alfadhel 

Yes, that's correct. 

I did not understand your question for last comment. 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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