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Observer
Observer
10,126 Views
Registered: ‎11-19-2013

Spartan 6 FPGA LX9 Microboard missing hardware co simulation file

Hi,
I am using ISE 14.7, and need to simulate the design on a Spartan 6 FPGA LX9 Microboard
using FUSE for hardware co-simulation (I am on Windows XP).
 
One of the options that is requied by the fuse for hardware co-simulation is "hwcosim_board"
where you identify the board to FUSE. The name for the board is found in the file "xltarget.m"
which can befound under
C:\Xilinx\14.7\ISE_DS\ISE\sysgen\plugins\compilation\Hardware Co-Simulation
In the above directory you  can see all the necessary boards such as AC701, SP601, SP605, etc.
You can find the needed name for the hardware co simulation in any of the above
directories for the appropriate name for the "hwcosim_board"

Unfortunately, I cannot see associated file for Spartan 6 FPGA LX9 Microboard. I thought
maybe SP601 or SP605 are the ones and thus have tried any of the following options
after checking the "xltarget.m" files but to no avail:
-hwcosim_board sp605-jtag
or
-hwcosim_board sp601-jtag
 
The FUSE gives me the following error message. Can anyone help please?:
 
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc6slx45t-3fgg484 -nt timestamp -intstyle xflow -uc hwcosim_top.ucf -sd
C:/Documentsand Settings/USER/MyDocuments/FPGA/Project -sd ../synth_wrapper
"C:\Documents and Settings\USER\My Documents\FPGA\Project\isim\hwcosim_tmp\jtag\xflow/hwcosim_top.ngc"
hwcosim_top.ngd
#----------------------------------------------#
ERROR:Portability:90 - Command line error:
Argument "C:\Documents and Settings\USER\My Documents\FPGA\isim\hwcosim_tm\jtag\xflow/hwcosim_top.ngc"

   has an invalid extension.  The valid extension is ".ngd".  If your file name

   has more than one "." in it you must explicitly enter the full file name with

   its extension.

 
 
 
 
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13 Replies
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Xilinx Employee
Xilinx Employee
10,120 Views
Registered: ‎07-11-2011

Hi,

 

Sysgen hardware cosim do not have ready plugins for Spartan6 LX9 board, you need to generate them using "New compilation Target" option in Sysgen token ->  Jtag co-sim

Please go through "Supporting New Boards through JTAG Hardware Co-Simulation" chapter in Sygen user guide for details and follow the step by step process

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sysgen_user.pdf

 

If you face any issues please visit relavant posts

http://community.em.avnet.com/t5/Spartan-6-LX9-MicroBoard/solved-System-Generator-HW-Co-Sim-with-the-LX9/td-p/4738

 

http://community.em.avnet.com/t5/Programmable-Logic/Xilinx-Hardware-Co-Simulation-over-USB/td-p/1060

 

 

 Hope this helps

  

Regards,

Vanitha.

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Observer
Observer
10,109 Views
Registered: ‎11-19-2013

Hi Vanitha,

 

Thanks for quick response. However, I am totally unfamiliar with Sysgen. It seem an interface

to Matlab, which is not my concern here... But then again, maybe it resolves my issue.

Where do you find Sysgen and how do you invoke it? In addition, in the document that you

mentioned, I found this secion "Installing Your Board for JTAG Hardware Co-Simulation"

on page 315 of the document. Is this the section that you had in mind?

 

(By the way, I am baffled that no one else seems to be using this board for a hardware

co simulation through JTAG....)

 

Thanks

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Xilinx Employee
Xilinx Employee
10,102 Views
Registered: ‎02-06-2013

Hi

 

DSP system generator HW cosimulation is different from the ISIM HW co simulation you want to use.

 

You can know more about Sysgen from link below which basically is for DSP designs.

 

http://www.xilinx.com/tools/sysgen.htm

 

For adding new boards in ISIM HW cosim,have a look at below link

 

http://www.xilinx.com/tools/feature/14_1_isim_hw_cosim_qrg.pdf

 

Hope it helps,

Regards,

Satish

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Observer
Observer
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Registered: ‎11-19-2013

Hi Satish,

You are correct. The link that you sent (http://www.xilinx.com/tools/feature/14_1_isim_hw_cosim_qrg.pdf) is

the one that I would need, and not the Sysgen. However, as you can see from slide 3 of the above link,

the Spartan 6 LX9 Microboard is missing from the list of "Supported Xilinx Boards". Slide #4, does

indicate on how to introduce a new board, but I am trying to avoid any mistakes. So is there an already

created file for this board so I do not have to re-invent the wheel as they say?

 

(I am not sure why Xilinx does not support this particular board as it is

listed obviously as a suggesed board by Xilinx here:

(http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm )

 

Thanks

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Xilinx Employee
Xilinx Employee
10,090 Views
Registered: ‎02-06-2013

Hi

 

A board file doesn't exist and that is the reason it is not shown in the list.

You need to create and add  this to the existing board files to use it. 

Regards,

Satish

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Observer
Observer
10,089 Views
Registered: ‎11-19-2013

Hi Satish,

Aah! In fact if you actually look at the file suggested in Slide #4 of what you sent me,

(i.e. that is if  you check $XILINX/sysgen/hwcosim/data/hwcosim.bsp ) you can actually see that

this board seems to be supported as can be seen on the line 437 of the file

(shown partly here):

  'sp601-jtag' => {
    'Description' => 'SP601 (JTAG)',
    'Vendor' => 'Xilinx',
    'Type' => 'jtag',
    'Part' => 'xc6slx16-2csg324',
    'Clock' => [
      {
        'Period' => 5

 

I tried following the steps suggested in your reference "Running Fro Project Navigator"

and I get exactly the same error message as before when I was running FUSE on the

comand line:

 

INFO:HWCoSim - Synthesizing design under test using XST
INFO:HWCoSim - Merging design under test netlists
INFO:HWCoSim - Synthesizing hardware co-simulation top-level
INFO:HWCoSim - Implementing hardware co-simulation top-level through NGDBuild, MAP and PAR
ERROR:HWCoSim - Program 'xflow' reported the following errors:
--------------------------------------------------------------------------------
ERROR:Portability:90 - Command line error: Argument "C:\Documents andSettings\USER\MyDocuments\FPGA\Project\isim\hwcosim_tmp\jtag\xflow/hwcosim_top.ngc"
   has an invalid extension.  The valid extension is ".ngd".  If your file name
   has more than one "." in it you must explicitly enter the full file name with
   its extension.
ERROR:Xflow - Program ngdbuild returned error code 1. Aborting flow execution...
--------------------------------------------------------------------------------
ERROR:HWCoSim - Program 'xflow' returned with a non-zero exit code 1. Please refer to log file 'C:\Documents and Settings\USER\My Documents\FPGA\Project\isim\hwcosim_tmp\jtag\xflow\xflow.log' for further details.
HDL wrapper and bitstream generation process failed.

Process "Simulate Behavioral Model" failed

 

So what is wrong? One possible hint could be the fact that the directory  'C:\Documents and Settings\USER\My Documents\FPGA\Project\isim, which was suggested in the above error , does NOT exist at all!!

 

Thanks

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Xilinx Employee
Xilinx Employee
9,979 Views
Registered: ‎02-06-2013

Hi

 

Some suggestions are

 

1.The board file for sp601 has a device of LX16(see the part) while your's is LX9 so still you need to build a correct board file for  your board.

 

2.Save your project in a location with out spaces(i.e Documents and settings) as we have seen issue with this.

 

3.If you still facing errors look for the error messages and search for the relevant posts and AR's obout the messages.

 

Hope it helps.

Regards,

Satish

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Observer
Observer
9,862 Views
Registered: ‎11-19-2013

Someone (the moderator?!) deleted my response to the above suggestion and I am not sure why. This is a Xilinx issue that needs to be addressed instead of pushing it under the rug. As I indicated in my deleted reply to the above suggestion:

1- Fixing the for LX9 did not solve the issue.

2- Moving the project to a directory name without a space seem to advance the co-simulation but it then stops complaining  of some unfounded errors of signals having multiple dirves.

3- I have searched and I cannot find any relavant post and AR's which address the issue. If anyone knows of a particular one, I would be more than happy to check it out.

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Xilinx Employee
Xilinx Employee
9,842 Views
Registered: ‎08-01-2008


System Generator provides a generic interface that uses JTAG and a Xilinx programming
cable (e.g., Parallel Cable IV or Platform Cable USB) to communicate with FPGA
hardware. This takes advantage of the ability of JTAG to extend System Generator's
hardware in the simulation loop capability to numerous other FPGA boards.

For more information, see section "Supporting New Boards through JTAG Hardware co-Simulation" in the System Generator User Guide.

Thanks and Regards
Balkrishan
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Observer
Observer
6,529 Views
Registered: ‎11-19-2013

The solution presented (see section "Supporting New Boards through JTAG Hardware co-Simulation") was already discussed and does not seem to be relevant (see above for a response from "vsrunga" the Moderator on 02-01-2014 09:23 AM, and the follow up responses).

All steps were taken correctly for supporting this board (and this is not a new board) yet errors seem to be persistent. This is a bug in the software (otherwise just moving the design to a directory whose name does not include any space would not advance the situation to another pitfall) that Xilins needs to address.

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Xilinx Employee
Xilinx Employee
6,505 Views
Registered: ‎08-01-2008

I have recheck the thread and its look like you have issue with FUSE. I would like to let you know FUSE is not Xilinx tool/application program.

I think FUSE is provided with Nallatach boards. can you please contact nallatech directly for these errors.
Thanks and Regards
Balkrishan
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Observer
Observer
6,466 Views
Registered: ‎11-19-2013

I am at awe for getting such a response from the Moderator:

 

1- The board that we are using for hardware co simulation is not OBVIOUSLY a Nallatech board, but one supported and advertised on Xilinx site.

 

2- The hardware cosimulation is part of the simulation strategy encouraged and thought by Xilinix (see for example  "ISim HW Co-Simulation 14.1 Quick Reference: www.xilinx.com/tools/feature/14_1_isim_hw_cosim_qrg.pdf‎)

So I am not sure why we had to contact Nallatech, but we did anyway and here is their response for anyone interested (No! this issue was not resolved, they just pushed the ball back to Xilinix court). And do please remember that we are not using their XtremeDSP Develpment Kit!!:

 

Hello,

 

If you purchased the XtremeDSP Development Kit VI directly from Nallatech, please provide the serial number of your kit so your support status can be checked.  You must have a valid support contract to receive support from Nallatech.

 

If you bought the XtremeDSP Development Kit VI from Xilinx or one of its distributors, then Xilinx will provide support.  If so, please direct any support inquiries for the XtremeDSP Development Kits through Xilinx using the webcase interface. As part of our distribution agreement with Xilinx, Xilinx provide the primary contact for any support enquiries with the XtremeDSP kit product.

 

This is described in the following answer record:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=16772.

 

You can open a support case from the following URL: http://support.xilinx.com/support/clearexpress/websupport.htm.

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Observer
Observer
6,462 Views
Registered: ‎11-19-2013

Sorry typo in the above reference:

see for example  "ISim HW Co-Simulation 14.1 Quick Reference: http://www.xilinx.com/tools/feature/14_1_isim_hw_cosim_qrg.pdf

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