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Observer
Observer
4,435 Views
Registered: ‎08-28-2014

Steps to create Satellite tuner

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Hello all.

 

I am new to ISE and Verilog.

 

I am charged with the responsibility to create a satellite tuner. I do not want anyone to write my code for me, but am not opposed to having examples posted. 

 

From my understanding so far my tuner will consist of a numerically controlled oscillator, multiplier using DDS, and a filter.

 

I have spent the past couple weeks teaching myself Verilog, because, none of the professors at my university have any experience.

 

I do not even know if this is the correct forum to post in.

 

Any direction to the right forum or resources will be appreciated and used voraciously.

 

Thank you for any help.

 

Aaron

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Observer
Observer
8,073 Views
Registered: ‎08-28-2014
Thank you balkris.

I will explore the documentation.

View solution in original post

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Teacher
Teacher
4,433 Views
Registered: ‎03-31-2012
my suggestion would be to use your favorite internet search engine to look for "verilog sdr software defined radio"
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Xilinx Employee
Xilinx Employee
4,415 Views
Registered: ‎08-01-2008
I would recommend you to use Vivado in place of ISE. In vivado as well you can use Verilog HDL

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug888-vivado-design-flows-overview-tutorial.pdf

In ISE you can use coregen or IP catalog , DDS, multiplier and filter IP are available in the IP catalog

https://www.xilinx.com/products/intellectual-property/fir_compiler.html

http://www.xilinx.com/products/intellectual-property/dds_compiler.html

http://www.xilinx.com/products/intellectual-property/multiplier.html
Thanks and Regards
Balkrishan
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Observer
Observer
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Registered: ‎08-28-2014
Thanks for a point in the right direction muzaffer.

I wish I could balkris. Besides outdated professors I have access to outdated technology. All I have is a Spartan 3E which is not compatible with Vivado from my understanding.
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Xilinx Employee
Xilinx Employee
4,405 Views
Registered: ‎08-01-2008
yes than you must have to use ISE if using Spartan 3E device
Thanks and Regards
Balkrishan
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Observer
Observer
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Registered: ‎08-28-2014
From your prior post and reading over the information I take it that the DDS compiler should be used to create a numerically controlled oscillator (NCO), the multiplier compiler for multiplying my input signal, and the FIR compiler for my filter.

All used to create the tuner.
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Xilinx Employee
Xilinx Employee
4,395 Views
Registered: ‎08-01-2008
yes thats true
Thanks and Regards
Balkrishan
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Observer
Observer
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Registered: ‎08-28-2014
Thank you balkris.

I will explore the documentation.

View solution in original post

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