Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎10-28-2010

Strange problem with System Generator FIR Compiler 7.2

Dear all,

We are experiencing a strange behaviour with the FIR Compiler block (v7.2) in System Generator. In certain bitstreams the IP does not give output signal (checked with ChipScope) even if the rest of its signals are correct. Sometimes, just re-synthesizing the Vivado project in which the IP generated with System Generator is instantiated (without changing any parameter on the IP or the project), the new generated bitstream works… other times it continues not working.

The IP is configured as “Single_rate”, 1 channel, 1 path, with the “Maximum_possible” Oversampling, Symmetric coefficients,  “Systolic_Multiply_Accumulate” architecture and Speed goal. We use 110 coefficients.

We have checked that all the generated timing constrains by SystemGenerator have been properly imported into the  Vivado project and that the generated implementations meets timing.

Is there any known bug that could explain this behaviour? Any clue on how to solve it?

Best regards




0 Kudos
1 Reply
Registered: ‎08-16-2018

If resythesizing the vivado project is removing the error, then there is no issue with System Generator (as System Generator only generates the file for implemenation). 

There must be some issue with Vivado itself. 

Can you try to use the generated project on some other Machine as well? 

Or reinstallation may resolve the issue. 

/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
0 Kudos