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dmittiga
Observer
Observer
544 Views
Registered: ‎03-08-2019

Support for Vector ASR in SSR library

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A block I frequently find myself desiring in System Generator is a Vector Addressable Shift Register. This does not exist in 2019.1. Are there any plans to provide this in any future versions?

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viswanad
Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎05-16-2018

Thanks for your message. We are planning to provide SSR support for ASR block in future release. I cannot commit any date, but the requirement is being considered.

Regards

Viswanadh

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viswanad
Xilinx Employee
Xilinx Employee
417 Views
Registered: ‎05-16-2018

Thanks for your message. We are planning to provide SSR support for ASR block in future release. I cannot commit any date, but the requirement is being considered.

Regards

Viswanadh

View solution in original post

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