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512 Views
Registered: ‎02-28-2011

Sygen Fifo bug in 2019.1?

Hi,

I just upgraded from System generator/Vivado 2016.4 (Matlab 2015a) to 2019.1 (Matlab 2018b).
There seems to be a bug with Fifo Genrator if the reset input is used:

ERROR: [Synth 8-448] named port connection 'srst' does not exist for instance 'core_instance0'...

This error appears for all IPs generated in Sysgen as long as the reset port for FIFOs is used.
All the FIFOs are used for cross domain clocking. I do not have any FIFO with reset in the same domain.

I compared the genrated code between the versions:

2016.4:

if (core_name0 == "ddr3_tfr_fifo_generator_v13_1_i1")
begin:comp1
ddr3_tfr_fifo_generator_v13_1_i1 core_instance1 (
.rd_clk(rd_clk),
.wr_clk(wr_clk),
.rst(rst),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout),
.full(full),
.empty(empty),
.rd_data_count(dcount)
);
end 

2019.1:

if (core_name0 == "ddr3_tfr_fifo_generator_i1")
begin:comp1
ddr3_tfr_fifo_generator_i1 core_instance1 (
.rd_clk(rd_clk),
.wr_clk(wr_clk),
.srst(rst),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout),
.full(full),
.empty(empty),
.rd_data_count(dcount)
);
end 

there is a clear difference between .srst(rst), and .rst(rst), port connections

after changing this manually in the entity declaration file, I can synthesis/compile successfully.

Looks like this is a bug?

Regards Markus

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3 Replies
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Xilinx Employee
Xilinx Employee
476 Views
Registered: ‎12-14-2017

Hi,

This is not reproducible for me in 2019.1 release. I tried with small fifo design and settings used are

  • Block memory configuration for FIFO
  • Compilation target in sysgen token is HDL netlist

Can you provide us .slx file to reproduce the problem, also state the fifo configuration and token settings ?

 

Regards,

Raju A. 

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449 Views
Registered: ‎02-28-2011

Hi Raju,

sorry for the late reply. I have been on vacation for the week.
I have attached a stripped down version with basically just the CDC logic and FIFO. It has the issue when code is generated.

Regards Markus

 

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Xilinx Employee
Xilinx Employee
430 Views
Registered: ‎12-14-2017

Hi,

Thanks for sharing the design.

It seems like this issue with Verilog and its a bug. As a work around, you can use VHDL instead of verilog in order to proceed with your design.

Hope it helps.