06-14-2019 05:04 AM
I just upgraded from System generator/Vivado 2016.4 (Matlab 2015a) to 2019.1 (Matlab 2018b).
There seems to be a bug with Fifo Genrator if the reset input is used:
ERROR: [Synth 8-448] named port connection 'srst' does not exist for instance 'core_instance0'...
This error appears for all IPs generated in Sysgen as long as the reset port for FIFOs is used.
All the FIFOs are used for cross domain clocking. I do not have any FIFO with reset in the same domain.
I compared the genrated code between the versions:
if (core_name0 == "ddr3_tfr_fifo_generator_v13_1_i1") begin:comp1 ddr3_tfr_fifo_generator_v13_1_i1 core_instance1 ( .rd_clk(rd_clk), .wr_clk(wr_clk), .rst(rst), .din(din), .wr_en(wr_en), .rd_en(rd_en), .dout(dout), .full(full), .empty(empty), .rd_data_count(dcount) ); end
if (core_name0 == "ddr3_tfr_fifo_generator_i1") begin:comp1 ddr3_tfr_fifo_generator_i1 core_instance1 ( .rd_clk(rd_clk), .wr_clk(wr_clk), .srst(rst), .din(din), .wr_en(wr_en), .rd_en(rd_en), .dout(dout), .full(full), .empty(empty), .rd_data_count(dcount) ); end
there is a clear difference between .srst(rst), and .rst(rst), port connections
after changing this manually in the entity declaration file, I can synthesis/compile successfully.
Looks like this is a bug?
06-19-2019 12:17 AM
This is not reproducible for me in 2019.1 release. I tried with small fifo design and settings used are
Can you provide us .slx file to reproduce the problem, also state the fifo configuration and token settings ?
06-24-2019 01:10 AM
06-24-2019 10:13 AM
Thanks for sharing the design.
It seems like this issue with Verilog and its a bug. As a work around, you can use VHDL instead of verilog in order to proceed with your design.
Hope it helps.