12-27-2017 09:09 AM
I am working with video based verilog design and use test pattern generator ip core which is given by Xilinx. I get this error message everytime when I try to synthesis the design. Googled answer gives only for custom designed ips. It seems the resquired file is missing from the repository with folder named hdl in resources. But this cannot fixed yet by replacing the file folder or re instantiating the ip in block design. I have licence for the video pattern generator ip. I'm using vivado 16.2 version and Zedboard. I will be grateful if anyone can give me a answer quickly.
01-13-2018 12:06 AM
Hi florentw,
It was not success with my all designs. Finally I decided to use global output product generation and it was ok up to now. Thank you for the concern and could you do what is suitable for this post since still I believe my problem is not fully solved.
Kind regards.
12-27-2017 02:06 PM
Hi,
Just guessing......has the IP core and its files been properly generated before instantiating it in your design?
Try re-generating the IP core (make sure there are no errors) and then integrate it in your design.
------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
12-27-2017 08:49 PM
HI,
Yes I tried several times by generating new tpg ip core into the design before. But it seems not working. However that required file is missed suddenly. This design worked well in previously. But all the design that I used tpg asked for same file now. But when I design a completely new simple design using tpg it is working. Problem is if I have to use that option I have to do all my works again for the current design. But I don't know it would work or not also.
Thanks.
12-27-2017 10:41 PM
01-04-2018 04:16 AM
Hi @asitha,
I have move your thread to the DSP and Video Board as it seems to be an issue with the TPG which is a video IP.
Regards,
Florent
01-04-2018 07:25 PM
Hi Florent,
Thank you for the kind attention and reply. I here attach my licence status and I am using my university licences. I tried short source path method that you have mentioned but not got the positive result. But I have noticed I can generate IP in global mode instead of out of context per ip mode and it worked many of the design. But failed in sometime with less frequency. Yesterday I tried with vivado 2017.2 and it seems quite ok with few times that I have checked. I will mark it in here if it is ok continuously with my designs.
Thank in advance.
01-12-2018 01:21 AM
HI @asitha,
I will mark it in here if it is ok continuously with my designs.
If the issue is solved for for you could you kindly close the topic by marking a respone as accepted solution (option -> accept as solution).
Thanks and Regards,
Florent
01-13-2018 12:06 AM
Hi florentw,
It was not success with my all designs. Finally I decided to use global output product generation and it was ok up to now. Thank you for the concern and could you do what is suitable for this post since still I believe my problem is not fully solved.
Kind regards.
01-15-2018 12:38 AM
Hi @asitha,
Could you mark your latest response as solution as it gives your workaround?
If you need to come back to this issue, it will be better to create a new topic.
Thanks,
Regards,