Synthesis failed error [Synth 8-439]

[asitha]

I am working with video based verilog design and use test pattern generator ip core which is given by Xilinx. I get this error message everytime when I try to synthesis the design. Googled answer gives only for custom designed ips. It seems the resquired file is missing from the repository with folder named hdl in resources. But this cannot fixed yet by replacing the file folder or re instantiating the ip in block design. I have licence for the video pattern generator ip. I'm using  vivado 16.2 version and Zedboard. I will be grateful if anyone can give me a answer quickly.

[dpaul24]

Hi,

Just guessing......has the IP core and its files been properly generated before instantiating it in your design?

Try re-generating the IP core (make sure there are no errors) and then integrate it in your design.

[asitha]

HI,

Yes I tried several times by generating new tpg  ip core into the design before. But it seems not working. However that required file is missed suddenly. This design  worked well in previously. But all the design that I used tpg asked for same file now. But when I design a completely new simple design using tpg  it  is working. Problem is if I have to use that option I have to do all my works again for the current design. But I don't know it would work or not also.

Thanks.

[asitha]

Hi,
thanks for reply. I use IP integrator in vivado to make the block design. I tried to figure out what was happening. Though I use Generate output products setting it do not create folder named hdl in the ip repositories in design. I tried many times. All folders except hld folder are generated. Could you help me with this?

[florentw]

Hi @asitha,

I have move your thread to the DSP and Video Board as it seems to be an issue with the TPG which is a video IP.

• Could you share a screehot of you vivado license manage showing the TPG license status? I am interested in version limit and host id match colums.
• Did you try with a newer version of vivado? If not could you?
• The issue might be due to the path length limit on windows (256 characters). Could you try to use a really short path (try to place your project directly under c:/)

Regards,

Florent

[asitha]

Hi Florent,

Thank you for the kind attention and reply. I here attach my licence status and I am using my university licences. I tried short source path method that you have mentioned but not got the positive result. But I have noticed I can generate IP in global mode instead of out of context per ip mode and it worked many of the design. But failed in sometime with less frequency. Yesterday I tried with vivado 2017.2 and it seems quite ok with few times that I have checked. I will mark it in here if it is ok continuously with my designs. 

Thank in advance.

[florentw]

HI @asitha,

I will mark it in here if it is ok continuously with my designs.

If the issue is solved for for you could you kindly close the topic by marking a respone as accepted solution (option -> accept as solution).

Thanks and Regards,

Florent

[asitha · Accepted solution]

Hi florentw,

It was not success with my all designs. Finally I decided to use global output product generation and it was ok up to now. Thank you for the concern and could you do what is suitable for this post since still I believe my problem is not fully solved.

Kind regards.

[florentw]

Hi @asitha,

Could you mark your latest response as solution as it gives your workaround?

If you need to come back to this issue, it will be better to create a new topic.

Thanks,

Regards,