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tsillanp
Adventurer
Adventurer
9,380 Views
Registered: ‎10-14-2013

SysGen 2013.3/14.7 not usable

How hard can it be...

 

1. ...to add 7-series support to Hardware Co-simulation -> New Compilation Target -> Targetable devices?! There's not even own compilation target makeover @ Vivado SysGen? =O

(yes, you already have ready made 7-series targets, not for ex. zedboard, and yes, you are able to edit the 7-series support by hand with text editor - but why would i be interested editing those by hand if you are not interested of implementing this simple feature?)

2. ...to add differential clock support for Bitstream target.

(yes, you are able also to do this hard way (ISE-project, own made clock wrapper, ...), but why would i be interested, if you have done this nice one-click feature to bitsream compilation, but not just updated it?)

3. ... to add choosable IOSTANDARD checkboxes to input/output gateways?! You are not able to make bitstream/hardware co-simulation if there's competing IOSTANDARDS (been there, done that, again manual editing. Why should I do manual editing if this could be just a simple GUI element?)

4. ... to add a choosable NON-MEMORY-MAPPED checkbox to input/output gateways for HWCOSIM? Yes, you are able to call some fancy functions or made it hard way making youre own hwcosim target (which, by the way doesn't support 7-series devices, oh, that was the 1.)

 

It's very annoying and very frustrating when a user needs to give development hints to the software manufacturer - and nothing happens. What's happening? Are you dropping the support of SysGen - because nothing has happened for the last 2 years to make the user experience better - and features like ethernet cosim supports only still 5-series chips?! No new hwcosim target support for Vivado SysGen - couple of years and we don't even see the hwcosim anymore?

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6 Replies
tsillanp
Adventurer
Adventurer
9,378 Views
Registered: ‎10-14-2013

Oh..

 

...and how hard can it be to implement proper error handling and asserts!? The "Fatal Internal Error" is a already a inside joke for everyone doing development with SysGen.

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tsillanp
Adventurer
Adventurer
9,361 Views
Registered: ‎10-14-2013

From 2013.3 release notes (SysGen):

"The customization of compilation targets is made easy through a new MATLAB® API

framework."

However, I can't find this from the GUI of SysGen or from documentation?

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tsillanp
Adventurer
Adventurer
9,348 Views
Registered: ‎10-14-2013

6. ... Digilent usb-jtag still not working under SysGen 14.7 HWCosim and ZedBoard - "Error locking JTAG programming cable." If you program it before hand on iMPACT and run skipping the programming, it runs flawless.

 

http://forums.xilinx.com/t5/DSP-Tools/HW-Co-simulation-on-ZC702-Using-Sysgen/td-p/361083

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balkris
Xilinx Employee
Xilinx Employee
9,322 Views
Registered: ‎08-01-2008

We do not have a GUI option called “New Compilation Target” in Vivado System Generator for DSP yet however the APIs to create a new compilation target have been documented in the User Guide

 

Open Sysgen, type xlDoc in the MATLAB command prompt. This should bring up the help document.

 

Navigate to ‘Creating Custom Compilation Target’ è ‘Creating a New Compilation Target’ è ‘Creating a New Board Target’.

 

This section shows you how to create a Zedboard target. Let me know if you have any questions about this.

Thanks and Regards
Balkrishan
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tsillanp
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Registered: ‎10-14-2013

7. ...Vivado SysGen doesn't support Shared Memory Blocks (HW COSIM).

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e_stoimenov
Visitor
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Registered: ‎03-16-2011

FYI : The Copy - > Paste is not possible  from the "help document".  

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