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walid_farid
Contributor
Contributor
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Registered: ‎04-14-2009

SysGen Block working at different clock frequencies

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Hello,

 

 Is it possible to make the Sysgen blocks run at different clock speeds? and if so how can it be done ?

 

 For example :

 I've a cordic_sine_cosine block which works at 10 MHz and the outputs of this block (the sines and cosines of the rad angles) are then connected to a another block which I need to run at a 100 MHz, so that for each sample from the cordic_sine_cosine block, an operation will be done ten times in the 2nd block.

 

Thanks,

 Walid F. Abdelfatah 

Message Edited by walid_farid on 08-25-2009 11:10 AM
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criley
Xilinx Employee
Xilinx Employee
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Registered: ‎08-16-2007

Yes it's possible to make differnt SysGen blocks run at different clock speeds using the Multiple Subsystem Generator block.  Then in each Subsystem you'll have a System Generator Token for which you can specify different FPGA Clocks. The SysGen User Guide has a few examples of doing this.

 

For the example you provided it sounds like you are more interested in using the "Up Sample" block rather than having multiple clock domains. 

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criley
Xilinx Employee
Xilinx Employee
5,152 Views
Registered: ‎08-16-2007

Yes it's possible to make differnt SysGen blocks run at different clock speeds using the Multiple Subsystem Generator block.  Then in each Subsystem you'll have a System Generator Token for which you can specify different FPGA Clocks. The SysGen User Guide has a few examples of doing this.

 

For the example you provided it sounds like you are more interested in using the "Up Sample" block rather than having multiple clock domains. 

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walid_farid
Contributor
Contributor
4,650 Views
Registered: ‎04-14-2009

Thank you .. I used an upsampling block to make both the blocks run at different frequencies. It can also be done using the Multiple-Subsystem generator,right ?

 

One more question : So are DCMs configured automatically after that or what ? and is this there another way to explicitly use a DCM ?

 

Thanks,

 Walid 

 

SW Versions : Xilinx ISE 10.1.3 , Matlab R2007b 

  

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