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Registered: ‎06-27-2013

Sysgen FFT9.0 ARESETn will not accept a signal with sample period different than 1

Hi there,


I have a sysgen design in which I send a QPSK modulated signal to an FFT V9 core.This modulated signal has a sample rate of 2 (as it takes two consecutive bits to create a QPSK signal), as well as all other signals used to configure this block.


Everything works great without a reset. However, the moment I try to use an ARESETn signal, I get in trouble. The system keeps giving me an error message telling me that the Normalized Sample Period for this port is 2, while it requires a Normalized Sample Period of 1. This makes little sense to me. As I said before, all signals that enter the FFT core have a sample period of 2, either because I use constants with such sample period, or because it receives signals that were downsampled to this period.


I tried to see what would happen if I used a signal with a sample period of 1 to drive this reset input. However, the result was that I got an output two times greater than my input (which kind of makes sense)


Any ideas on how to drive this ARESETn with a signal with the same sample period of all other signals entering the FFT core?





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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

Can you please share test case to reproduce this issue
Thanks and Regards
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