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Visitor darking2539
Visitor
214 Views
Registered: ‎09-01-2018

Sysgen IPCORE

Hi. Has anyone ever worked with Xilinx system generator and IP Integrator I want to design add bit shown in below photo

I want to number plus a number( eg. 5+5=10) and show result by xil_printf using write C code by using SDK.

Thankyou

SYSGEN_IPCORE.jpg
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1 Reply
Moderator
Moderator
180 Views
Registered: ‎08-16-2018

Re: Sysgen IPCORE

You can export the SysGen project as Vivado project using "System generator token". Open the token and select the device (and testbench option) and press generate. The vivado project will be saved at location "<project directory>\netlist\ip_catalog". 

 

After that you can use the IP with SDK to show the results. 

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