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m7888
Observer
Observer
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Registered: ‎06-27-2015

Sysgen multi clock domain issue : Block may only be used in a subsystem with a single clock domain.

Hi,

I get an error when trying to update a sysgen model containing multi clock domains. The error points to a masked block which has programatic access to xilinx blocks. The error points to all "Slice" blocks in the specific subsystem and says that only one clock domain is permitted for the subsystem. But there is actually one clock domain in that subsystem. There is even no "Constant" block in it. The error is this:

 

Block may only be used in a subsystem with a single clock domain.

 

 

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m7888
Observer
Observer
696 Views
Registered: ‎06-27-2015

By the way, I am using VIVADO 2017.4

and something strage solves the issue. When I comment out the programmatic access to the inner blocks, the error fades away. But I cant (and I dont want) to do this for actual implementation. So please help if you have ever encountered such problem.

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