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Adventurer
Adventurer
9,644 Views
Registered: ‎11-12-2010

System Generation error when generating with "Synthesized Checkpoint" option

Hello community

 

We have a huge design in sysGen that is generated correctly in "HDL Netlist" and "IP catalog" options.

But when we try to generate it with "Synthetized Checkpoint", after a very long compilation time it appears 168  error messages like showed above. This is the first one.

 

 

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Start Cross Boundary Optimization
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ERROR: [Common 17-223] Fail to read message file F:/MercuryUltra/BoundingBoxes/Target/Synthesized Checkpoint/bounding_boxes.runs/synth_1/.Xil/Vivado-5156-/realtime/tmp/7AE672A0.rtd.pb. Please check permission of the directory and existence of the file.

 

Please note that F:/MercuryUltra/BoundingBoxes/Target folder is the target directory of SysGen project. Also note that subfolder F:/MercuryUltra/BoundingBoxes/Target/Synthesized Design have a space into. This subfolder is created by SysGen or Vivado and I suspect is part of the problem

 

Anyone can help?

 

Best regards

 

 

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Adventurer
Adventurer
9,640 Views
Registered: ‎11-12-2010

 
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Xilinx Employee
Xilinx Employee
9,602 Views
Registered: ‎05-07-2015

hi @david.quinones

 

Seems like a folder access permission issue. Can you try and open sysgen 2015.4 with "Run as Administrator" option and try again?

Thanks
Bharath
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Adventurer
Adventurer
9,582 Views
Registered: ‎11-12-2010

Hello @nagabhar

 

I have executed SysGen 2015.4 as administrator and I obtain the same issues.

I have verified that there is enough disk space (42GB).

 

For more information I attach vivado.log to the message.

 

Best regards

 

David Q

 

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Xilinx Employee
Xilinx Employee
9,578 Views
Registered: ‎08-01-2008

http://www.xilinx.com/support/answers/64394.html

Thanks and Regards
Balkrishan
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Adventurer
Adventurer
9,563 Views
Registered: ‎11-12-2010

"Provide Clock Enable Clear Pin" is unchecked.

This answer record do not seem to be related with this case

Best regards
David Q.

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Xilinx Employee
Xilinx Employee
9,532 Views
Registered: ‎05-07-2015

HI @david.quinones

 

Can you check if there are any *.rtd.pb files present in 
"F:/MercuryUltra/BoundingBoxes/Target/Synthesized Checkpoint/bounding_boxes.runs/synth_1/.Xil/Vivado-6832-/realtime/tmp/" folder?

Can you please share you sysgen model file here with us? so that we can check it our end?

Thanks
Bharath
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Adventurer
Adventurer
9,518 Views
Registered: ‎11-12-2010

Hello @nagabhar

 

Folder F:/MercuryUltra/BoundingBoxes/Target/Synthesized Checkpoint/bounding_boxes.runs/synth_1/.Xil/ is empty, so there is no directories or files inside.

Probably, the problem is located at the space in .../Synthesized Checkpoint/... folder. This directory is created by SysGen or Vivado during generation. Historicaly, Xilinx tools had problems with spaces in file paths. Any way to change to a .../Synthesized_Checkpoint/... folder?

 

The sysgen model is a main part of our whole design and I can´t share it. Sorry. No problem to share log or report files.

 

Best regards

 

David Q

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Adventurer
Adventurer
9,448 Views
Registered: ‎11-12-2010

Hi!

 

Any news about this bug?

 

Could I obtain a .cdp file from project generated in the hdl netlist mode?

 

Best regards

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Newbie
Newbie
8,799 Views
Registered: ‎03-04-2016

I have the same problem. Any solutions?

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Newbie
Newbie
8,147 Views
Registered: ‎03-12-2016

I just developed the same issue.

 

I'm developing a set of IP modules for a project and I inadvertently tried to create 67*8 (536) 32-bit registers for my AXI-lite interface.  It should have only been 67+8 (75) registers.  Even though a good number of the registers will not be used/implemented in the design, something in trying to create such a large number of 32-bit registers must have caused the issue to pop-up during synthesis.

 

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Newbie
Newbie
8,145 Views
Registered: ‎03-12-2016

I just developed the same issue.

 

I'm developing a set of IP modules for a project and I inadvertently tried to create 67*8 (536) 32-bit registers for my AXI-lite interface.  It should have only been 67+8 (75) registers.  Even though a good number of the registers will not be used/implemented in the design, something in trying to create such a large number of 32-bit registers must have caused the issue to pop-up during synthesis.

 

Just to mention this.  I initially replied to the wrong post.

 

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Newbie
Newbie
7,432 Views
Registered: ‎04-04-2016

i have the same error message -

when i delete enough of the one large block - i get the error to go away and synthesis completed 

i have tried flat and no heirarchy in the synthesis runs  - but i get the same error message -

 

Is this a weird error message that is in essence a capacity issue??

i never have more than 10% utilization when the run completes -

 

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Explorer
Explorer
7,211 Views
Registered: ‎10-24-2008

Please check to ensure that you do not have any spaces in your project path and/or Xilinx installation path.  We have confirmed that this can result in this specific error message (ERROR: [Common 17-223] Fail to read message file).

 

Kind regards,

Quenton

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Adventurer
Adventurer
7,201 Views
Registered: ‎11-12-2010

You are right

 

The problem is that SysGen create a folder called "Synthesized Checkpoint" with a space in the middle. I'm suspecting about this fact from the beggining, but I don´t know any way to change this folder name.

 

Best regards

 

David Quiñones

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Xilinx Employee
Xilinx Employee
7,198 Views
Registered: ‎08-01-2008

This is bug in sysgen and to workaround generate netlist from sysgen and perform timing in Vivado tool
Thanks and Regards
Balkrishan
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Participant
Participant
6,789 Views
Registered: ‎05-25-2016

Is there a way to change the naming of the generated directory from "Synthesized Checkpoint" to "Synthesized_Checkpoint" by modifing a script in vivado201X.X/Vivado/201X.X/scripts/sysgen/matlab?

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Adventurer
Adventurer
6,787 Views
Registered: ‎11-12-2010

It would be a great step forward!! ;)

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Visitor
Visitor
6,596 Views
Registered: ‎05-27-2016

I just ran into this same problem using SysGen 2016.1 and a "synthesized checkpoint" output.

 

However, a small design that I have works through this flow even though the directory that SysGen creates "Synthesized Checkpoint" has a space in it. A larger design that I have causes SysGen to throw an error when it cannot find a particular file several directories down past the "Synthesized Checkpoint" directory.

 

Given this experience, it doesn't seem like it's the space in the directory name that is causing the error, but something else.

 

 

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Participant
Participant
6,564 Views
Registered: ‎05-25-2016

It looks like "Generate" creates all required tcl scripts before starting the vivado batch processes.

Therefore I killed the hanging process, renamed directory "Synthesized Checkpoint" to "Synthesized_Checkpoint" and modified the corresponding variable CustomProjectDir in ProjectGeneration.tcl from "Synthesized Checkpoint" to "Synthesized_Checkpoint". Now the command "source ProjectGeneration.tcl -notrace" (see vivado.jou) finished successfully and generated the desired synthesized checkpoint.

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Highlighted
5,506 Views
Registered: ‎06-25-2016

Generated files produced for an IP customization. They can include HDL, constraints, and simulation targets. The XCI file stores the configuration and constraint options that are user-specified during customization. During generation, these customizations are used to produce the files that are used during synthesis and simulation.

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Observer
Observer
4,967 Views
Registered: ‎02-26-2016

I reproduced the problem with Vivado 2015.4.

 

Even the System Generator documentation says that spaces are not allowed (UG897 v2015.4 page 183):

 

"Note: Be aware that the target_name cannot contain spaces. After the class is created, you can add
spaces to the target_name property of the class."

 

You can fix it here by changing the target_name property

 

C:\Xilinx\Vivado\2015.4\scripts\sysgen\matlab\plugins\compilation\@Synthesized_Checkpoint\Synthesized_Checkpoint.m

 

Is this fixed in newer versions?