05-06-2013 01:44 PM
I am trying to get use System Generator co-simulation on the AC701 (Artix 7) evaluation board with the ISE 14.5 tools. From the system generator user guide, I see that to get IO working I need to create "non-memory mapped gateway blocks". What is the best way to do this? I have tried the following approaches:
1) Use the system generator wizard. To do this, I attempted to create a new co-simulation hardware target and then add my IO in the wizard. However, the Artix 7 doesn't appear as a targetable device -- so I am unable to proceed.
2) Manually modify the AC701 JTAG co-simulation target. I have found the target folder ...\sysgen\plugins\compilation\Hardware Co-Simulation\AC701\ and I was planning to edit the UCF file, xml file, the ac701_target.m file, the ac701_postgeneration.m file, etc. However, all that exists in this folder is "xltarget.m", which doesn't point to any of the files that are typically generated when you create a custom compilation target... So I don't know where to go to add the gateway block information?
Where is system generator looking to get the ac701 target information?
Any help would be greatly appreciated!
05-17-2013 02:40 PM
Okay, I managed to get JTAG hw-cosimulation running with the board specific I/O. To get it going, I had to create a custom compilation target using a different FPGA and then edit the generated .m, .ucf, and .xml files to change the FPGA part to the artix 7 and add the board specific I/O. I created a library that includes the various user I/O.
If anyone is interested, I have attached a zip file with the files needed to target this board. To use it, unzip the folder into your hardware co-simulation folder in the install directory, i.e.:
(after unziping you will have a folder: C:\Xilinx\14.5\ISE_DS\ISE\sysgen\plugins\compilation\Hardware Co-Simulation\AC701io\ with several files in it.)