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talon
Observer
Observer
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Registered: ‎02-05-2019

System Generator: HDL Black Box include mem files.

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I have successfully managed to wrap up most of my HDL cores in black boxes in Simulink. They can be successfully simulated and synthesized with System Generator. I've done all this using this user guide.

One block I am having issue wrapping up is a FIR filter for which I have specified window coefficients in .mem files for the BRAM's to load. Now, to add all the VHDL source files the black box needs for compilation/simulation, I used the following commands in the black box configuration MATLAB script (see page 186 of the linked document):

addFile("filename");
addFileToLibrary("filename","library");

 These commands successfully add VHDL source files to the Vivado project (in the correct library) that System Generator produces. If I try to include a '.mem' file using the above commands however, it does not add it and synthesis down the line will complain that I do not have the required memory files in my Vivado project (obviously).

No where in that linked document is there mention of how to include memory files so I am reaching out to see whether I am missing something or there is a way in which one ought to overcome this hurdle.

Thank you.  

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vkanchan
Xilinx Employee
Xilinx Employee
176 Views
Registered: ‎09-18-2018

Hi @talon ,

This is because m-script for sysgen does not recognize the .mem files currently. MEM files were introduced with XPM and this support is missing in sysgen. An enhancement request is filed to support this.

This issue can be worked around by adding the absolute path of the mem file in the HDL generic declaration as well as in the m-script as below

GENERIC(
g_adr_w : NATURAL := 9;
g_dat_w : NATURAL := 22;
g_nof_words : NATURAL := 2**9;
g_rd_latency : NATURAL := 2; -- choose 1 or 2
g_init_file : STRING := "C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem";
g_ram_primitive : STRING := "auto" --choose auto, distributed, block, ultra
);

 

 

this_block.addGeneric('g_init_file','STRING','"C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem"');

When the netlist is generated from Sysgen, the code will refer the mem file in the given path and synthesize fine. Only drawback is if the code is ported to other machine or if the file is moved, the mem file location needs to be provided again.

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vkanchan
Xilinx Employee
Xilinx Employee
177 Views
Registered: ‎09-18-2018

Hi @talon ,

This is because m-script for sysgen does not recognize the .mem files currently. MEM files were introduced with XPM and this support is missing in sysgen. An enhancement request is filed to support this.

This issue can be worked around by adding the absolute path of the mem file in the HDL generic declaration as well as in the m-script as below

GENERIC(
g_adr_w : NATURAL := 9;
g_dat_w : NATURAL := 22;
g_nof_words : NATURAL := 2**9;
g_rd_latency : NATURAL := 2; -- choose 1 or 2
g_init_file : STRING := "C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem";
g_ram_primitive : STRING := "auto" --choose auto, distributed, block, ultra
);

 

 

this_block.addGeneric('g_init_file','STRING','"C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem"');

When the netlist is generated from Sysgen, the code will refer the mem file in the given path and synthesize fine. Only drawback is if the code is ported to other machine or if the file is moved, the mem file location needs to be provided again.

View solution in original post

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