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andyknight09
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Registered: ‎12-10-2013

System Generator HDL Netlist XDC Timing Constraints

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I have just been through the process of generating HDL netlists for a design using System Generator 2013.3. This creates a Vivado 2013.3 project which includes the generated HDL source files and two constraint files.

 

The first constraint file (rampcounter_clock.xdc) specifies the global clock:

 

#######################################################################
# This file is automatically generated from System Generator for DSP #
# design. Consult the documentation before making any modifications #
#######################################################################
# Global Clock Constraints
create_clock -name clk -period 20.00000000 [get_ports clk]

 

The second constraint file (rampcounter.xdc) contains the following:

 

#######################################################################
# This file is automatically generated from System Generator for DSP #
# design. Consult the documentation before making any modifications #
#######################################################################
set rateCe8 default_clock_driver_rampcounter/xlclockdriver_8/pipelined_ce.ce_pipeline[1].ce_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp
set rateCells8 [get_cells -of [filter [all_fanout -flat -endpoints [get_pins $rateCe8/Q]] IS_ENABLE]]
set_multicycle_path -from $rateCells8 -to $rateCells8 -setup 8
set_multicycle_path -from $rateCells8 -to $rateCells8 -hold 7

 

However when I attempt to synthesize this project I receive the following critical warning:

 

[Designutils 20-964] Command failed: can't read "rateCells8": no such variable. 

 

I am used to working in ISE rather than Vivado so XDC constraint files are still a bit alien to me but it looks like rateCells8 has been declared. What is the reason for this warning message? Should I be using these autogenerated constraint files as they are or do I need to modify them?

 

I understand that for the final design I will need to specify all of my other constraints so I think the global constraint will be moved into that top level constraint file but the constraints in the second file I would expect to keep as they are.

 

Cheers,

 

Andy

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

It looks like Vivado is not reading the Sysgen generated constarints with variables.

Please replace rateCe8 and rateCells8 with actual nets in your counters.xdc and see how it goes.

I see this works at my end.

 

Attached the .xdc for reference.

 

Hope this clarifies.

 

 

Regards,

Vanitha.

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vsrunga
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Registered: ‎07-11-2011

Hi,

 

Data base says that the warning occurs when there are no create_clock constarints corresponding to ratecells8, can you show us the full warning message with xdc line number ?

 

If you could share us the design or steps to reproduce the warning (if in case this is Xilinx demo design) we will look in to it and suggest you accordinly.

 

Yes, I too believe the constraints in the second file to keep as they are when the respective modules are untouched.

 

 

Regards,

Vanitha.

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andyknight09
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Sure, the full message is:

 

Processing XDC Constraints
Parsing XDC File [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter.xdc]
can't read "rateCells8": no such variable
CRITICAL WARNING: [Designutils 20-964] Command failed: can't read "rateCells8": no such variable. [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter.xdc:7]
can't read "rateCells8": no such variable
CRITICAL WARNING: [Designutils 20-964] Command failed: can't read "rateCells8": no such variable. [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter.xdc:8]
Finished Parsing XDC File [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.runs/synth_1/.Xil/rampcounter_propImpl.xdc].
Resolution: To avoid this warning, exclude constraints listed in [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.runs/synth_1/.Xil/rampcounter_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter_clock.xdc]
Finished Parsing XDC File [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter_clock.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.srcs/constrs_1/imports/sysgen/rampcounter_clock.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.runs/synth_1/.Xil/rampcounter_propImpl.xdc].
Resolution: To avoid this warning, exclude constraints listed in [C:/Zynq/NetlistRampCounter/hdl_netlist/rampcounter.runs/synth_1/.Xil/rampcounter_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

 

See previous post for the complete constraint files.

 

The design process I went through was:

 

1) Create Matlab 2013b Simulink model including System Generator 2013.3 token and Xilinx blocks (in fact this model was ported from an older version of Matlab and System Generator). NOTE: I selected the following options which may or may not be of interest:

Compilation: HDL Netlist

Part: Zynq Eval Board

Language: VHDL

Library: rampcounterlib

 

FPGA Clock period: 20ns

Clock pin location: <empty>


2) Click the "Generate" button on the System Generator properties

3) Open the resulting project (in NetlistRampCounter/hdl_netlist) using Vivado 2013.3

4) Click Run Synthesis

 

At which point I noticed the critical warning messages.

 

If there is a tutorial with source files that you could point me to which is known not to produce this warning message then could you please point me at it?

 

Cheers,

 

Andy

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Below is the AR I am referring not any tutorial.

 

http://www.xilinx.com/support/answers/57265.html

 

Seems like the error is same but the design might be different based on which you have to add the create clock constraint in the top level file and I beleive this is deisgn depedent warning.

 

If your design has any core requires they require  a create clock at the system level.

Generally any core with async FIFO Gen sub core requires create clock on top level clocks so underlying XDCs can use that info to configure multicycle paths internally. In this case user design must have creat_clock on all clocks so underlying IP constraints can use that information.

 

Can you upload your design so that we will check and get back ?

 

 

Regards,

Vanitha.

 

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vsrunga
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Hi,

 

Clock pin location: <empty>

>> The other though is please select a clock pin so that the tool may create the constraint for you.

and are you abel to generate bitstream/NGC netlsit from Sysgen itself with out invoking the Vivado project and see teh same erorr?

 

 

Regards,

Vanitha.

 

 

 

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andyknight09
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OK, I tried setting the clock pin location (ad pin locations for all of my other gateways) but that had no effect. I have created a simle test model which exhibits the same critical warnings and attached it to this post. Hopefully you will be able to replicate the critical warnings during synthesis.

 

Regarding generating the bitstream from SysGen without using Vivado I don't know how to do that. We have never created an entire design in SysGen before so have always used the netlist output in ISE to build the SysGen model into a larger design. 

 

Cheers,

 

Andy

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andyknight09
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Just to explain the attachment. I have included:

1) The test model I created which just has two counters that each run at different rates
2) The System Generator netlist output folder

When I open the Vivado project and synthesise I see two critical warnings like the ones mentioned in my first post.

Cheers,

Andy
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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Thanks for trying the suggestions.

Able to see the critical warnings in your attached  files, will get back to you with my findings ASAP.

 

 

Regards,

Vanitha.

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vsrunga
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Registered: ‎07-11-2011

Hi,

 

It looks like Vivado is not reading the Sysgen generated constarints with variables.

Please replace rateCe8 and rateCells8 with actual nets in your counters.xdc and see how it goes.

I see this works at my end.

 

Attached the .xdc for reference.

 

Hope this clarifies.

 

 

Regards,

Vanitha.

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andyknight09
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Registered: ‎12-10-2013

Thanks for that Vanitha. I've just made those changes in my project and I no longer get those critical warnings.

 

Is this a bug in Vivado 2013.3 then? I would have expected System Generator 2013.3 to create constraints that Vivado 2013.3 could read :).

 

Cheers,

 

Andy

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi Andy,

 

Yes, this could be a bug but I just checked in 2013.4 build and it goes fine with the variables.

So I think this could be added as known issue in Sysgen + Vaivado 2013.3

 

 

Regards,

Vanitha.

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andyknight09
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OK, thanks for checking that. I will use the workaround until we move onto 2013.4.

Cheers,

Andy
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