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canisio
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Registered: ‎06-01-2021

System Generator SSR FFT spurious spikes depending on combinations of N and SSR

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Hello all,

I'm trying to implement an SSR FFT using sysgen. I'm modifying the example project "sysgenSSRIFFT" which is for N=1024 and SSR=4. I was able to successfully convert this project to a forward FFT, however, when I increase N and/or SSR, the resulting spectrum has spurious spikes outside of the expected frequency component (plots attached). At the begging I though it was a problem related to the sync of the parallel output, so I decide to just dump the output to the workspace and reassemble it using Matlab after the simulation, but the problem persists.

I'm using a pure complex sinusoidal as test input and noticed that this problem occurs periodically, with different intensity, depending on a combination of N and SSR. For example, for N=4196 and SSR=16, there are only a half dozen spurious at multiple integers of the the test frequency, however, when N=8192 or SSR = 32, the undesired outputs increase significantly. My goal here is N=8192 and SSR=32, which obviously outputs a lot of "garbage". I can upload the model file if needed.

Is this a known issue for the FFT algorithm in general? An error on the FFT block? Or problems in the SSR implementation? Overflow?

Are the SSR blocks intended to be used in real applications or are they a kind of "beta test"?

 

 

N_2048_SSR_32.jpg
N_4096_SSR_16.jpg
N_4096_SSR_32.jpg
1 Solution

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi ,

I have attached the R2020a version of the model

View solution in original post

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vkanchan
Xilinx Employee
Xilinx Employee
606 Views
Registered: ‎09-18-2018

Hi @canisio ,

What is the device that you are targetting here ?  and what is the data width configured on input gateways and in SSR FFT block ?

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canisio
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Registered: ‎06-01-2021

Hi @vkanchan 

Thanks for your help.

The device selected on the sysgen token is the ZCU106 evaluation platform. There is only the SSR FFT block and the input width is 18bit (Fix_18_16). The scaling input is 13bit ufix, but it is set to zero right now. Output is 26 (Fix_26_16).

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @canisio ,

This mostly looks like an issue due to overflow.  Referring to the documentation, there should be at least log2N bits more to avoid overflow due to bit growth.

I have a small design that I modified for N=8192 and SSR=32  and feed a sine wave, and the output is reflected in the desired bin. I am attaching the design here.

ssr_fft_8192.jpg
canisio
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Registered: ‎06-01-2021

HI @vkanchan 

Thanks for the update,

I was already playing with the dynamic range of the input and it definitely looks like an overflow issue. I'll test your design ASAP.

Since you mentioned the documentation... The documentation for SSR blocks is extremely simple. How can we know details about the parallelism and the architecture of these blocks? Is there any extra source for it?

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canisio
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Registered: ‎06-01-2021

@vkanchancould you please re-save the model so I can open in Simulink 2020a? Thank you.

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vkanchan
Xilinx Employee
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Registered: ‎09-18-2018

Hi ,

I have attached the R2020a version of the model

View solution in original post

canisio
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Registered: ‎06-01-2021

Thank you @vkanchan , it works. I still have some questions

Could you please explain why does your project has an extra delay at the "N-sample enable"?(z2 instead of z1)

Why it is active low if the documentation says it is active high? Maybe to deactivate the block after N/SSR clocks?

Why are all those delays needed before the gateways in? One could say that it is to break the critical path, but they're outside the FPGA.

Could you also explain what the "unbuffer" subsystem do? Actually I'm trying to understand how the output should be reassembled after the SSRFFT. In other words, what is the correspondent bin for each parallel output. I'm sorry for insisting, the documentation for the SSR is poor.

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

HI @canisio ,

Extra delay on the N-sample is to avoid the first frame from the buffer on the input data paths. The first frame from the buffer would be all zero value samples and this would not be a valid input frame.

In_valid becomes low after N/SSR blocks because only one input frame of data is considered here. 

The delays before the gatewaysin were for simple handling of the data inputs from the frame buffers in this example.

The unbuffer subsystem in this example feeds each "SSR" vector data into a delay line of length 'N' so it can access all the 'N' values at the same time after "N/SSR" clock cycles, which is indicated by the tlast.