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Sam_K
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Registered: ‎01-28-2021

System Generator- Synthesize on Cmod-S7 FPGA

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Hello,

I am beginning with Xilinx System Generator to synthesize my logic onto Cmod-S7. To start with, I would like to synthesize an AND gate with two inputs from push buttons and an output to led. I wasn't able to find where the I/O constraints could be specified in XSG. Could you please point me to any tutorials.

Thank you.

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meherp
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Registered: ‎08-16-2018

Hi @Sam_K 
You can not apply the IO contraint from the sysgen. 
You need to generate the Vivado design from sysgen. 
Then, write the constraints for gateway in (i.e. push button) and gateway out (i.e. LED block) in Vivado. And then generated the bitstream.  


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

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meherp
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Moderator
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Registered: ‎08-16-2018

Hi @Sam_K 
You can not apply the IO contraint from the sysgen. 
You need to generate the Vivado design from sysgen. 
Then, write the constraints for gateway in (i.e. push button) and gateway out (i.e. LED block) in Vivado. And then generated the bitstream.  


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...

View solution in original post

Sam_K
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Registered: ‎01-28-2021

Hi @meherp , thanks for your reply.

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