05-23-2018 02:43 AM
System generator is a DSP tool from Xilinx that enables the use of Mathworks model-based simulink design environment for FPGA designs. Same description follows for Model composer also.
The basic difference between System generator and Model composer from higher level is with the output that both tools generates. SysGen generates the RTL directly., whereas, Model composer generates the Vivado HLS compatible C/C++ code. This code can be used in downstream tools to generate RTL followed by gate level netlist till bitstream generation.
Refer to UG1262 for Model composer and UG897 for System generator for more information
06-01-2018 10:24 AM
But in system generator, HLS ip-cores can be imported as well.
So, is there any substantial difference in performances, or other things?
It seems as if the two tools are quite identical, except in the output products.
06-13-2018 09:33 AM
This is how I describe the difference between SysGen and Model Composer:
07-23-2018 06:23 AM
07-24-2018 01:45 PM - edited 07-24-2018 02:58 PM
To answer your first question, for complex data types, Model Composer supports all the data types it supports for non-complex data types. Below is a screen shot of three examples.
On SysGen, I mean telecommunication systems, such as modulators, demodulators, filtering, encoding, etc. DSP is Digital Signal Processing.
Hope this helps.