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deepwavebill
Adventurer
Adventurer
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Registered: ‎08-09-2018

System Generator black box errors

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I have a System Generator model where I am trying to add a Black Box model for a state machine that is coded up in Verilog. I get errors when I go through the elaborate step when running the System Generator simulation. I get the following errors listed:

Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2858] localparam 'IDLE' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:10]
ERROR: [VRFC 10-2858] localparam 'PRD0_CNT0' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:11]
ERROR: [VRFC 10-2858] localparam 'PRD0_CNT1' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:12]
ERROR: [VRFC 10-2858] localparam 'PRD1_CNT0' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:13]
ERROR: [VRFC 10-2858] localparam 'PRD1_CNT1' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:14]
ERROR: [VRFC 10-2858] localparam 'PRD1_CNT2' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:15]
ERROR: [VRFC 10-2858] localparam 'PRD1_CNT_FNL' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:16]
ERROR: [VRFC 10-2858] localparam 'PRD_CNT_FNL' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:17]
ERROR: [VRFC 10-2858] localparam 'PRD_CNT_VLD' cannot be overwritten [C:/Users/kirscwm2/AppData/Local/Temp/xlsim607dce57/hdl_netlist/xelab.srcs/sources_1/imports/xlsim607dce57/prdminen_sm_07a06e94b666ae8545466d9f4cf61254.v:18]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

In the verilog file these were the states of the state machine.

// State machine
parameter IDLE = 9'b000000001;
parameter PRD0_CNT0 = 9'b000000010;
parameter PRD0_CNT1 = 9'b000000100;
parameter PRD_CNT_VLD = 9'b000001000;
parameter PRD_CNT_FNL = 9'b000010000;
parameter PRD1_CNT0 = 9'b000100000;
parameter PRD1_CNT1 = 9'b001000000;
parameter PRD1_CNT2 = 9'b010000000;
parameter PRD1_CNT_FNL = 9'b100000000;

I have included my verilog design file. Any idea of how to get around this issue? The .m file generated by the Black Box did not work either until I edited it. I will include it also. Maybe this is not correct. Hard to say based on the documentation that Xilinx provides. Thanks.

 

Bill

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vkanchan
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎09-18-2018

Hi @deepwavebill ,

I checked the m-file containing the configuration. It can be noticed that the parameter used to define states are also added as a generic in this file.

These parameters cannot be used outside the scope of module, however m-file picks this up. this can be due to how the Verilog file is parsed. 

Comment out the following section of code in m-file :

% this_block.addGeneric('IDLE','integer','1');
% this_block.addGeneric('PRD0_CNT0','integer','2');
% this_block.addGeneric('PRD0_CNT1','integer','4');
% this_block.addGeneric('PRD_CNT_VLD','integer','8');
% this_block.addGeneric('PRD_CNT_FNL','integer','16');
% this_block.addGeneric('PRD1_CNT0','integer','32');
% this_block.addGeneric('PRD1_CNT1','integer','64');
% this_block.addGeneric('PRD1_CNT2','integer','128');
% this_block.addGeneric('PRD1_CNT_FNL','integer','256');
%this_block.addGeneric('prd_cnt_lsbs','','');

 

I added the configuration file which I used to successfully simulate the black box module at my end.

View solution in original post

4 Replies
vkanchan
Xilinx Employee
Xilinx Employee
192 Views
Registered: ‎09-18-2018

Hi @deepwavebill ,

Does the Verilog module attached, work fine in Vivado simulation ? This is to ensure that issues in Verilog code are ruled out

 

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deepwavebill
Adventurer
Adventurer
172 Views
Registered: ‎08-09-2018

Hi vkanchan,

I have fully verified the Verilog code with behavioral simulation in Vivado. Thanks.

Bill

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vkanchan
Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎09-18-2018

Hi @deepwavebill ,

I checked the m-file containing the configuration. It can be noticed that the parameter used to define states are also added as a generic in this file.

These parameters cannot be used outside the scope of module, however m-file picks this up. this can be due to how the Verilog file is parsed. 

Comment out the following section of code in m-file :

% this_block.addGeneric('IDLE','integer','1');
% this_block.addGeneric('PRD0_CNT0','integer','2');
% this_block.addGeneric('PRD0_CNT1','integer','4');
% this_block.addGeneric('PRD_CNT_VLD','integer','8');
% this_block.addGeneric('PRD_CNT_FNL','integer','16');
% this_block.addGeneric('PRD1_CNT0','integer','32');
% this_block.addGeneric('PRD1_CNT1','integer','64');
% this_block.addGeneric('PRD1_CNT2','integer','128');
% this_block.addGeneric('PRD1_CNT_FNL','integer','256');
%this_block.addGeneric('prd_cnt_lsbs','','');

 

I added the configuration file which I used to successfully simulate the black box module at my end.

View solution in original post

deepwavebill
Adventurer
Adventurer
101 Views
Registered: ‎08-09-2018

Hi vkanchan,

That fixed it. Thanks for figuring out the issue.

Bill

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