UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor dzungnh95
Visitor
236 Views
Registered: ‎01-23-2019

System Generator simulation correctness

Jump to solution

Hi,

I'm designing an IIR filter on Zynq7. I use SysGen to create the filter ip core.

To implement IIR filter, I use all AddSub, Mult and Constant (for coefficients) with the floating point option and zero latency.

When I simulate it on SysGen (MATLAB), the result is exactly what I expect.

However, when I implement all on my development kit, the result is so weird. I want to ask whether the SysGen behavior is exactly the same with the real behavior?

Thank you,

Dung

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
220 Views
Registered: ‎09-18-2018

Re: System Generator simulation correctness

Jump to solution

Hi @dzungnh95 ,

Sysgen is bit and cycle accruate hardware modelling tool. So the simulation will match that of hardware.

Can you check if the correct clocking parameters are passed in your sysgen token ?

which version of vivado/sysen is being used ?

Did you check the behavioral simulation of the generated code in Vivado simulator ? Any difference here ?

If the board is a Xilinx evaluation board , can you check the Hardware Co-sim and report any differences ?

View solution in original post

1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎09-18-2018

Re: System Generator simulation correctness

Jump to solution

Hi @dzungnh95 ,

Sysgen is bit and cycle accruate hardware modelling tool. So the simulation will match that of hardware.

Can you check if the correct clocking parameters are passed in your sysgen token ?

which version of vivado/sysen is being used ?

Did you check the behavioral simulation of the generated code in Vivado simulator ? Any difference here ?

If the board is a Xilinx evaluation board , can you check the Hardware Co-sim and report any differences ?

View solution in original post