02-19-2019 09:16 AM
I have a System Generator black box with some VHDL code that I am trying to simulate in Simulink. The data is not getting passed into the HDL code from System Generator correctly for some reason. Single bit inputs look OK but all mutli-bit inputs are incorrect. For instance I have an input num_sym_frame which is std_logic_vector(15 downto 0) and the input value is 1384 decimal (568 hex) from a constant block with type UFix_15_0. In the ModelSim wave viewer it shows up as 4096 decimal (1000 hex). Any idea what might be happening here?
02-21-2019 09:52 PM
It's probable due to that different data format. Can you change the sysgen data format to fix_15_0?
Also if you run HDL co-sim with Vivado simulator, does it make difference?
02-25-2019 08:03 AM
Using fix_15_0 doesn't change anything. I still get the wrong values in ModelSim. I selected Vivado as the simulator, but it doesn't open up when I run the Simulink model and I can't figure out why.
02-27-2019 06:04 PM
It sounds like the tools have an issue. Are you able to run simulation with SysGen model, which does not have a blackbox? Are you able to run Vivado simulation and get the expected outputs?
03-01-2019 07:28 AM
Yes, SysGen works fine without black boxes. Vivado simulation works fine too. It seems to be something with passing data between SysGen and Modelsim. I am using Modelsim DE-2019.1.
03-03-2019 06:28 PM
If you do not use SysGen, can you run behavrioal simulation successfully with Vivado and Modelsim? This is to make sure that this version of Modelsim is compatible with Vivado.