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martincamp
Visitor
Visitor
706 Views
Registered: ‎01-22-2019

System generator Black box with Modelsim problem

I have a System Generator black box with some VHDL code that I am trying to simulate in Simulink.  The data is not getting passed into the HDL code from System Generator correctly for some reason.  Single bit inputs look OK but all mutli-bit inputs are incorrect.  For instance I have an input num_sym_frame which is std_logic_vector(15 downto 0) and the input value is 1384 decimal (568 hex) from a constant block with type UFix_15_0.  In the ModelSim wave viewer it shows up as 4096 decimal (1000 hex).  Any idea what might be happening here?

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nathanx
Moderator
Moderator
650 Views
Registered: ‎08-01-2007

It's probable due to that different data format. Can you change the sysgen data format to fix_15_0?

Also if you run HDL co-sim with Vivado simulator, does it make difference?

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martincamp
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Registered: ‎01-22-2019

Using fix_15_0 doesn't change anything.  I still get the wrong values in ModelSim.  I selected Vivado as the simulator, but it doesn't open up when I run the Simulink model and I can't figure out why.

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nathanx
Moderator
Moderator
604 Views
Registered: ‎08-01-2007

It sounds like the tools have an issue. Are you able to run simulation with SysGen model, which does not have a blackbox? Are you able to run Vivado simulation and get the expected outputs?

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martincamp
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Visitor
582 Views
Registered: ‎01-22-2019

Yes, SysGen works fine without black boxes.  Vivado simulation works fine too.  It seems to be something with passing data between SysGen and Modelsim.  I am using Modelsim DE-2019.1.

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nathanx
Moderator
Moderator
565 Views
Registered: ‎08-01-2007

If you do not use SysGen, can you run behavrioal simulation successfully with Vivado and Modelsim? This is to make sure that this version of Modelsim is compatible with Vivado.

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