05-18-2020 08:01 AM
My DSP (System generator design flow) needs to buffer a full image to external memory DDR3 on board. For this purpose, I want to create an AXI4 memory-mapped interface on DSP to get access to DDR via MIG ip. Since the limited resource, I want the DSP "works" directly to MIG without using any DMA. I have read UG897 but it did not say much about AXI4 full.
I am very beginer level on System generator, If you have any advices on how to do OR simple examples, please guide me.
Thank you so much.
06-01-2020 01:07 AM
Hi @eos_huyvq ,
The "Gateway" block in system generator can be implemented as normal port or as a AXI-4 Lite interface. The Sysgen block can be imported into Vivado as an IP and the interfaces can be converted to the AXI4 full interface using the AXI protocol converter in the Vivado IP catalog. if the memory map interfaces are desired.