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Contributor
Contributor
11,219 Views
Registered: ‎03-08-2014

System generator error

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Hi...

I am working on an image processing algorithm using system generator. In my design i am using three black boxes.

I am getting following errors when running simulation

 

Error 0001: Rates and types converged for the feedback path through t...
Blocks: 'exp_low_pass/Address Generator', et al.
Error 0002: Internal Block Error: Set illegal rate
Block: 'exp_low_pass/Address Generator'
Error 0003: Internal Block Error: Set illegal rate
Block: 'exp_low_pass/Address Generator'
Error 0004: Internal Block Error: Set illegal rate
Block: 'exp_low_pass/Address Generator'
Error 0005: Internal Block Error: Set illegal rate
Block: 'exp_low_pass/Address Generator'

 

Attached is the snipet of my design.Plz tell me how to fix the above mentioned problems. 

 

Thanks & Regards

Punit Kumar

design.PNG
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Xilinx Employee
Xilinx Employee
15,198 Views
Registered: ‎07-11-2011

Re: System generator error

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Hi,

 

It looks like your design has feed back loops and hence the tool is finding difficluty to derive the rate, better to use assert blocks and retry.

 

Please check this links

http://forums.xilinx.com/t5/DSP-Tools/Assert-block-in-a-feedback-loop/td-p/217601

 

http://forums.xilinx.com/t5/DSP-Tools/Error-in-rates-and-types/td-p/416637

 

Edit:

You may also need to use data type converison blocks specified in Sysgen reference guide 

 

Hope this helps

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
11,198 Views
Registered: ‎07-11-2011

Re: System generator error

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Hi,

 

It looks like you are connecting ufix_18_0 pixenb_addr to en port which I guess is boolean, please change the data type so that they match the type and recheck

 

Also visit relavant links

 

http://forums.xilinx.com/t5/DSP-Tools/Error-occurred-during-quot-Rate-and-Type-Error-Checking-quot/td-p/406421

 

http://forums.xilinx.com/t5/DSP-Tools/Black-box-error/td-p/408399

 

Hope this helps

 

Regards,

Vanitha

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Contributor
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Registered: ‎03-08-2014

Re: System generator error

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Hi...Vanitha

 

Thanks for reply.

As you said I checked the connections and they are correctly connected and even I think i have set correct data types. But I am not sure about the rates. Can you plz tell me how to set the rates in blackbox.

I am sending you all the data and codes. Can you plz look at it and tell me what else  I am doing wrong.

 

Thanks & Regards

Punit Kumar

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Teacher
Teacher
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Registered: ‎08-14-2007

Re: System generator error

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Hi,

in the sysgen start up guide there's a section describing how to make the datarates visible.

Maybe that helps you understanding what you are dealing with to find a solution.

 

Have a nice simulation

  Eilert

 

 

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Contributor
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Registered: ‎03-08-2014

Re: System generator error

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Hi Eilert,

 

Attached is the snippet of the model in which datarates are visible. Can you plz tell me how to change the datarates.In the model I am using three black boxes namely address generator, mean filter, and controller.

 

Thanks & Regards

Punit Kumar

 

 

snippet.PNG
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Teacher
Teacher
11,171 Views
Registered: ‎08-14-2007

Re: System generator error

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Hi,

I'm not sure what you have enabled, but it shows just 100 and -100 on the inputs. (negative datarates???)

 

I expected something like what can be seen in chapter 4 of the sysgen getting started guide (UG639) Pg. 54:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/sysgen_gs.pdf

 

Have a nice simulation

  Eilert

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Contributor
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Registered: ‎03-08-2014

Re: System generator error

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Hi,

 

I went through that guide and tried that too but I was getting error it wasn't showing anything . There is an option available in system generator block :system generator -> general -> Block Icon Display -> sample frequencies; I selected that option and Igot that result.

 

Thanks & Regards

Punit Kumar

 

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Xilinx Employee
Xilinx Employee
15,199 Views
Registered: ‎07-11-2011

Re: System generator error

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Hi,

 

It looks like your design has feed back loops and hence the tool is finding difficluty to derive the rate, better to use assert blocks and retry.

 

Please check this links

http://forums.xilinx.com/t5/DSP-Tools/Assert-block-in-a-feedback-loop/td-p/217601

 

http://forums.xilinx.com/t5/DSP-Tools/Error-in-rates-and-types/td-p/416637

 

Edit:

You may also need to use data type converison blocks specified in Sysgen reference guide 

 

Hope this helps

 

Regards,

Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Xilinx Employee
Xilinx Employee
11,146 Views
Registered: ‎08-01-2008

Re: System generator error

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use  command  xlUpdateModel('mdlname', 'assert')  to update your model, you can use the xlUpdateModel command at the Matlab command prompt. You can have xlUpdateModel automatically insert assert blocks for the rate propagation (data type propagation blocks must be placed manually) by using the following syntax. 

> xlUpdateModel('mdlname', 'assert') 

 

Make sure to add the single quotation marks, and replace mdlname with the name of your .mdl file. 

 

You can also access the xlUpdateModel help by typing the following. 

> help xlUpdateModle

 

Hope it will help

Thanks and Regards
Balkrishan
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Contributor
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Registered: ‎03-08-2014

Re: System generator error

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Hi Vanitha

 

Thanks lots for your help.

Still I am getting one more Problem "Bool type output port dout gets indeterminate value." I am using Win 64 professional,MATLAB 2012b, ISE 14.4. Plz help.

 

Thanks and Regards

Punit 

 

model.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: System generator error

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For Feedback path you must have assert block.

Thanks and Regards
Balkrishan
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Re: System generator error

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Hi

 

Actually I have changed my logic and removed the feedback path. Now I  am facing another problem that i have mentioned in my last post. Could you plz tell me how to solve this.

 

Thanks & Regards

Punit

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Xilinx Employee
Xilinx Employee
8,333 Views
Registered: ‎07-11-2011

Re: System generator error

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Hi,

 

I would suggest you to upgrade to 14.7  + Matlab R2013b inorder to avoid any known issues of tools

A bit old but please check if it helps

http://www.xilinx.com/support/answers/36919.htm

 

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: System generator error

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After removing the feedback path are you getting similar error or else. You can the demo design and see if you can reproduce with some other designs. In case all the design have same issue then most likely issue is with your installation, environmental variable settings etc.
Thanks and Regards
Balkrishan
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Contributor
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Re: System generator error

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Hi

 

I am getting "Bool type output port q gets indeterminate value" I am getting the error in another model  herein attached.

model.PNG
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Contributor
Contributor
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Re: System generator error

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Hi

 

The problem has magically gone on converting input and output to delay from bool to UFix_1_0 and UFix_1_0  to bool respectively. Thanks lots to all for their help.

 

Thanks and Regards

Punit 

model1.PNG