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scott_sysgen
Visitor
Visitor
1,474 Views
Registered: ‎10-01-2020

System generator simulation hangs/crashes

I'm currently running Vivado 2019.1 with matlab 2019a using system generator. I have run into a situation several times now where certain combinations of precision between blocks will result in a sysgen simulation hanging at the "initializing" step,which is the last step of preparation before a simulation runs.  

I ran the simulink debugger, and the last function it executes before hanging is

S-Function.SetupRunTimeResources

No error messages from either matlab or Vivado. No error file created.  It has just apparently crashed, and the only way out is to kill matlab

It isn't officially a matlab crash, so there is no matlab crashdump file or anything.  It just hangs.

If I change the output precision (total bits and binary point) to certain other values, it starts and runs fine.  Trouble is, with no error message, it's impossible to know what is causing the problem, or what the troublesome combinations are.  All I am trying to do is compensate for filter bitgrowth 

Thanks for any help.

Scott

 

 

11 Replies
vkanchan
Xilinx Employee
Xilinx Employee
1,395 Views
Registered: ‎09-18-2018

Hi @scott_sysgen ,

Which blocks are using in your design ?  is it possible to share it ?

 

 

 

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scott_sysgen
Visitor
Visitor
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Registered: ‎10-01-2020

I am using a ROM to hold complex numbers.  The current precision is set to total bits =10, binary point = 8.  If I change the binary point or increase total number of bits, I see the problem described.  There is nothing in the ROM core that indicates a maximum bit width.  I am using a total of 128 ROMS (64 real, 64 imaginary)

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azad.jalali
Observer
Observer
1,199 Views
Registered: ‎10-26-2017

I've also been having this issue with two different designs, it's so frustrating. One of them is extremely complex and it has been basically impossible to debug when it hangs, so I have to work extremely slowly/incrementally to make sure I'm not suddenly breaking the simulation. There is often no obvious reason why there should be an issue, so it feels completely arbitrary.

I really don't understand how people successfully use System Generator for large designs. Is everyone just tolerating these issues? Is there a debug window that I'm missing with actual feedback? Having to force quit Simulink 10 times and randomly change things to get my model to run is not a great workflow.

drjohnsmith
Teacher
Teacher
1,183 Views
Registered: ‎07-09-2009

I feel your pain,
I gave up on MATLAB / Simulink code a while back.

The Matlab generated HDL code is terrible,
I'm amazed the Xilinx tools manage to synthesise it at all.

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jmdewart
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Registered: ‎05-15-2018

@vkanchanany news on this?  How we can we troubleshoot the issue?  I'm experience the same thing with this environment:

Ubuntu 18.04.2  LTS

Vivado 2020.2

MATLAB R2020a

 

I've attached a model and diagnostic report from sysgen.  The _sysgen.log file is empty as the simulation never starts.  I see ~/.Xilinx/Sysgen/SysgenVivado/lnx64.o fill with some files but the simulation hangs on initializing.

azad.jalali
Observer
Observer
999 Views
Registered: ‎10-26-2017

FYI everyone, I have gotten around this with some luck. By happenstance more than anything, I changed three things at once and haven't had time to experiment to know which one fixed it, but now my design runs reliably and I am coincidentally much more keen on SysGen now

  1. Switched from Redhat (Linux) to Windows 10
  2. Under Model Settings, set Solver Selection to: Variable-Step, discrete
  3. I was simulating with "Accelerator" before, switched to "Normal"

Hopefully it was #2 or #3 that fixed it, since those are easy changes to make! If someone has a chance to try any of these, let me know your results. When I have a chance I will also experiment.

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jmdewart
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Registered: ‎05-15-2018

Thanks for the reply and suggestions.  Discrete step/normal mode doesn't resolve the issue.  Maybe windows does but I'm hoping to find a solution for Linux.

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vkanchan
Xilinx Employee
Xilinx Employee
831 Views
Registered: ‎09-18-2018

 Hi @jmdewart ,

Thank you for sharing the model. We have identified the cause of this issue being the multiple ROM blocks present in the design. Once the number of ROM blocks exceeds a certain number of instances, the tool slows down.

We are checking this further and will update once a fix /workaround is found to it.

jmdewart
Observer
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Registered: ‎05-15-2018

Thanks for the update, looking forward to a solution.

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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi All,

Here are a few observations after debugging this issue with the example design provided by @jmdewart .

1. The issue is not seen on Windows.

2. The issue is not seen on Linux OS with MATLAB R2019a version or older.

3. The issue is reproducible with MATLAB R201b and higher ( irrespective of Vivado version) on Linux.

Checking it further to find the root cause of the issue.

zengin
Visitor
Visitor
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Registered: ‎02-21-2021

Any news from this issue?

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