05-24-2017 11:35 AM
Our goal is to take synthesized SystemVerilog code from design team and implement it in System Generator for complete mixed signal system simulation in Simulink and subsequent emulation on FPGA. My research shows that at present SystemVerilog is not supported in System Generator and I see no obvious work around.
Is there a way to get System Verilog code into System Generator?
For Xilinx team, Is there a plan to implement SystemVerilog support in System Generator? If yes, what is the timeline?
06-19-2017 12:07 AM
06-23-2017 12:26 AM